soc/amd/cezanne,vc/cezanne: Implement svc_write_postcode

This will allow verstage to write post codes.

BUG=b:215425753
TEST=Boot guybrush and verify PSP post codes are printed
22-01-31 15:12:03.214 (S3->S0)
22-01-31 15:12:03.214   03 04 0f 0e f0 f1 f2 01 10 a0 a2 <--new

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ceee8fcb094f462de99c07aef8e96425d9c3270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61522
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h

@@ -51,6 +51,7 @@
 #define SVC_SHA                             0x69
 #define SVC_CCP_DMA                         0x6A
 #define SVC_SET_PLATFORM_BOOT_MODE          0x6C
+#define SVC_WRITE_POSTCODE                  0x6D
 
 struct mod_exp_params {
 	char		*pExponent;	// Exponent address