Remove leftover Intel i82801a support
Change-Id: Ibcecd34d552cd1a4d945c74996d47223a39dc5c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
@@ -1,22 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
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||||
##
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## This program is distributed in the hope that it will be useful,
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||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_INTEL_I82801AX
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bool
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select IOAPIC
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select HAVE_HARD_RESET
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select USE_WATCHDOG_ON_BOOT
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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@@ -1,32 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y)
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ramstage-y += i82801ax.c
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ramstage-y += ac97.c
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ramstage-y += ide.c
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ramstage-y += lpc.c
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ramstage-y += pci.c
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ramstage-y += smbus.c
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ramstage-y += usb.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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romstage-y += early_smbus.c
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endif
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@@ -1,57 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Tyan Computer
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* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801ax.h"
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static struct device_operations ac97_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = 0,
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.scan_bus = 0,
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.enable = i82801ax_enable,
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};
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/* 82801AA (ICH) */
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static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
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};
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static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
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};
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/* 82801AB (ICH0) */
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static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
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};
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static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
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.ops = &ac97_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
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};
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@@ -1,36 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The i82801ax code supports: 82801AA/82801AB (ICH/ICH0).
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
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#define SOUTHBRIDGE_INTEL_I82801AX_CHIP_H
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#include <stdint.h>
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struct southbridge_intel_i82801ax_config {
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u8 pirqa_routing;
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u8 pirqb_routing;
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u8 pirqc_routing;
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u8 pirqd_routing;
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u8 ide0_enable;
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u8 ide1_enable;
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};
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#endif
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@@ -1,55 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Tyan Computer
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* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
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* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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||||
*
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <southbridge/intel/common/smbus.h>
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#include "i82801ax.h"
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void enable_smbus(void)
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{
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pci_devfn_t dev;
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/* Set the SMBus device statically (D31:F3). */
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dev = PCI_DEV(0x0, 0x1f, 0x3);
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/* Set SMBus I/O base. */
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pci_write_config32(dev, SMB_BASE,
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SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
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/* Set SMBus enable. */
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pci_write_config8(dev, HOSTC, HST_EN);
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/* Set SMBus I/O space enable. */
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pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
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/* Disable interrupt generation. */
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outb(0, SMBUS_IO_BASE + SMBHSTCTL);
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/* Clear any lingering errors, so transactions can run. */
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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printk(BIOS_DEBUG, "SMBus controller enabled\n");
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}
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int smbus_read_byte(u8 device, u8 address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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@@ -1,46 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005 Digital Design Corporation
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* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
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* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
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||||
*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include "i82801ax.h"
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void i82801ax_enable(struct device *dev)
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{
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u16 reg16, index;
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struct device *lpc_dev;
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/* Search for the 82801AA/AB LPC device (D31:F0) on PCI bus 0. */
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lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
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if (!lpc_dev)
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return;
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index = PCI_FUNC(dev->path.pci.devfn);
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reg16 = pci_read_config16(lpc_dev, FUNC_DIS);
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reg16 &= ~(1 << index); /* Enable device. */
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if (!dev->enabled)
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reg16 |= (1 << index); /* Disable device, if desired. */
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pci_write_config16(lpc_dev, FUNC_DIS, reg16);
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}
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struct chip_operations southbridge_intel_i82801ax_ops = {
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CHIP_NAME("Intel ICH/ICH0 (82801AA/AB) Series Southbridge")
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.enable_dev = i82801ax_enable,
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};
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@@ -1,93 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
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||||
*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
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#define SOUTHBRIDGE_INTEL_I82801AX_I82801AX_H
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#if !defined(__PRE_RAM__)
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#include "chip.h"
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void i82801ax_enable(struct device *dev);
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#else
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void enable_smbus(void);
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int smbus_read_byte(u8 device, u8 address);
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#endif
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#define SMBUS_IO_BASE 0x0f00
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#define PMBASE_ADDR 0x0400
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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#define GEN_STA 0xd4
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#define RTC_CONF 0xd8
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#define GEN_PMCON_3 0xa4
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define ACPI_EN (1 << 4)
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x58 /* GPIO Base Address Register */
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#define GPIO_CNTL 0x5C /* GPIO Control Register */
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#define GPIO_EN (1 << 4)
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define FUNC_DIS 0xF2
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#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */
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#define LPC_EN 0xE6 /* LPC IF Enables */
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// TODO: FDC_DEC etc.
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#define SBUS_NUM 0x19
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#define SUB_BUS_NUM 0x1A
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#define SMLT 0x1B
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#define IOBASE 0x1C
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#define IOLIM 0x1D
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#define MEMBASE 0x20
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#define MEMLIM 0x22
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#define CNF 0x50
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#define MTT 0x70
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#define PCI_MAST_STS 0x82
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#define TCOBASE 0x60 /* TCO Base Address Register */
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#define TCO1_CNT 0x08 /* TCO1 Control Register */
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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/* IDE Timing registers (IDE_TIM) */
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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/* IDE_TIM bits */
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#define IDE_DECODE_ENABLE (1 << 15)
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/* SMBus */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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#endif
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@@ -1,71 +0,0 @@
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/*
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||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2005 Tyan Computer
|
||||
* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
|
||||
* Copyright (C) 2005 Digital Design Corporation
|
||||
* (Written by Steven J. Magnani <steve@digidescorp.com> for Digital Design)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
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||||
#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "i82801ax.h"
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typedef struct southbridge_intel_i82801ax_config config_t;
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|
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static void ide_init(struct device *dev)
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||||
{
|
||||
u16 reg16;
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config_t *conf = dev->chip_info;
|
||||
|
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reg16 = pci_read_config16(dev, IDE_TIM_PRI);
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||||
reg16 &= ~IDE_DECODE_ENABLE;
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||||
if (!conf || conf->ide0_enable)
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||||
reg16 |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
|
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(reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
|
||||
pci_write_config16(dev, IDE_TIM_PRI, reg16);
|
||||
|
||||
reg16 = pci_read_config16(dev, IDE_TIM_SEC);
|
||||
reg16 &= ~IDE_DECODE_ENABLE;
|
||||
if (!conf || conf->ide1_enable)
|
||||
reg16 |= IDE_DECODE_ENABLE;
|
||||
printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
|
||||
(reg16 & IDE_DECODE_ENABLE) ? "on" : "off");
|
||||
pci_write_config16(dev, IDE_TIM_SEC, reg16);
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.scan_bus = 0,
|
||||
.enable = i82801ax_enable,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2411,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_ide __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2421,
|
||||
};
|
||||
@@ -1,301 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2003 Linux Networx
|
||||
* Copyright (C) 2003 SuSE Linux AG
|
||||
* Copyright (C) 2005 Tyan Computer
|
||||
* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <pc80/isa-dma.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include "i82801ax.h"
|
||||
|
||||
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
|
||||
|
||||
#define NMI_OFF 0
|
||||
|
||||
typedef struct southbridge_intel_i82801ax_config config_t;
|
||||
|
||||
/* PIRQ[n]_ROUT[3:0] - IRQ Routing (ISA compatible)
|
||||
* 0x00 - 0000 = Reserved
|
||||
* 0x01 - 0001 = Reserved
|
||||
* 0x02 - 0010 = Reserved
|
||||
* 0x03 - 0011 = IRQ3
|
||||
* 0x04 - 0100 = IRQ4
|
||||
* 0x05 - 0101 = IRQ5
|
||||
* 0x06 - 0110 = IRQ6
|
||||
* 0x07 - 0111 = IRQ7
|
||||
* 0x08 - 1000 = Reserved
|
||||
* 0x09 - 1001 = IRQ9
|
||||
* 0x0A - 1010 = IRQ10
|
||||
* 0x0B - 1011 = IRQ11
|
||||
* 0x0C - 1100 = IRQ12
|
||||
* 0x0D - 1101 = Reserved
|
||||
* 0x0E - 1110 = IRQ14
|
||||
* 0x0F - 1111 = IRQ15
|
||||
*
|
||||
* PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
|
||||
* 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
|
||||
* 1 - The PIRQ is not routed to the 8259.
|
||||
*/
|
||||
|
||||
#define PIRQA 0x03
|
||||
#define PIRQB 0x04
|
||||
#define PIRQC 0x05
|
||||
#define PIRQD 0x06
|
||||
|
||||
/*
|
||||
* Use 0x0ef8 for a bitmap to cover all these IRQ's.
|
||||
* Use the defined IRQ values above or set mainboard
|
||||
* specific IRQ values in your devicetree.cb.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* Enable ACPI I/O range.
|
||||
*
|
||||
* @param dev PCI device with ACPI and PM BAR's
|
||||
*/
|
||||
static void i82801ax_enable_acpi(struct device *dev)
|
||||
{
|
||||
/* Set ACPI base address (I/O space). */
|
||||
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
|
||||
|
||||
/* Enable ACPI I/O range decode and ACPI power management. */
|
||||
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
|
||||
}
|
||||
|
||||
/**
|
||||
* Set miscellanous static southbridge features.
|
||||
*
|
||||
* @param dev PCI device with I/O APIC control registers
|
||||
*/
|
||||
static void i82801ax_enable_ioapic(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = pci_read_config32(dev, GEN_CNTL);
|
||||
reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
|
||||
reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
|
||||
reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
|
||||
reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
|
||||
pci_write_config32(dev, GEN_CNTL, reg32);
|
||||
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
|
||||
|
||||
set_ioapic_id(VIO_APIC_VADDR, 0x02);
|
||||
|
||||
/*
|
||||
* Select Boot Configuration register (0x03) and
|
||||
* use Processor System Bus (0x01) to deliver interrupts.
|
||||
*/
|
||||
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
|
||||
}
|
||||
|
||||
static void i82801ax_enable_serial_irqs(struct device *dev)
|
||||
{
|
||||
/* Set packet length and toggle silent mode bit. */
|
||||
pci_write_config8(dev, SERIRQ_CNTL,
|
||||
(1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
|
||||
pci_write_config8(dev, SERIRQ_CNTL,
|
||||
(1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
|
||||
/* TODO: Explain/#define the real meaning of these magic numbers. */
|
||||
}
|
||||
|
||||
static void i82801ax_pirq_init(struct device *dev)
|
||||
{
|
||||
u8 reg8;
|
||||
config_t *config = dev->chip_info;
|
||||
|
||||
reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
|
||||
pci_write_config8(dev, PIRQA_ROUT, reg8);
|
||||
|
||||
reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
|
||||
pci_write_config8(dev, PIRQB_ROUT, reg8);
|
||||
|
||||
reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
|
||||
pci_write_config8(dev, PIRQC_ROUT, reg8);
|
||||
|
||||
reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
|
||||
pci_write_config8(dev, PIRQD_ROUT, reg8);
|
||||
}
|
||||
|
||||
static void i82801ax_power_options(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
int pwr_on = -1;
|
||||
int nmi_option;
|
||||
|
||||
/* power after power fail */
|
||||
/* FIXME this doesn't work! */
|
||||
/* Which state do we want to goto after g3 (power restored)?
|
||||
* 0 == S0 Full On
|
||||
* 1 == S5 Soft Off
|
||||
*/
|
||||
pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
|
||||
printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off");
|
||||
|
||||
/* Set up NMI on errors. */
|
||||
byte = inb(0x61);
|
||||
byte &= ~(1 << 3); /* IOCHK# NMI Enable */
|
||||
byte &= ~(1 << 2); /* PCI SERR# Enable */
|
||||
outb(byte, 0x61);
|
||||
byte = inb(0x70);
|
||||
|
||||
nmi_option = NMI_OFF;
|
||||
get_option(&nmi_option, "nmi");
|
||||
if (nmi_option) {
|
||||
byte &= ~(1 << 7); /* Set NMI. */
|
||||
outb(byte, 0x70);
|
||||
}
|
||||
}
|
||||
|
||||
static void gpio_init(struct device *dev)
|
||||
{
|
||||
pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
|
||||
pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
|
||||
}
|
||||
|
||||
static void i82801ax_rtc_init(struct device *dev)
|
||||
{
|
||||
uint8_t reg8;
|
||||
uint32_t reg32;
|
||||
int rtc_failed;
|
||||
|
||||
reg8 = pci_read_config8(dev, GEN_PMCON_3);
|
||||
rtc_failed = reg8 & RTC_BATTERY_DEAD;
|
||||
if (rtc_failed) {
|
||||
reg8 &= ~(1 << 1); /* Preserve the power fail state. */
|
||||
pci_write_config8(dev, GEN_PMCON_3, reg8);
|
||||
}
|
||||
reg32 = pci_read_config32(dev, GEN_STA);
|
||||
rtc_failed |= reg32 & (1 << 2);
|
||||
cmos_init(rtc_failed);
|
||||
|
||||
/* Enable access to the upper 128 byte bank of CMOS RAM. */
|
||||
pci_write_config8(dev, RTC_CONF, 0x04);
|
||||
}
|
||||
|
||||
static void i82801ax_lpc_route_dma(struct device *dev, uint8_t mask)
|
||||
{
|
||||
uint16_t reg16;
|
||||
int i;
|
||||
|
||||
reg16 = pci_read_config16(dev, PCI_DMA_CFG);
|
||||
reg16 &= 0x300;
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (i == 4)
|
||||
continue;
|
||||
reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
|
||||
}
|
||||
pci_write_config16(dev, PCI_DMA_CFG, reg16);
|
||||
}
|
||||
|
||||
static void i82801ax_lpc_decode_en(struct device *dev)
|
||||
{
|
||||
/* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
|
||||
* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
|
||||
* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
|
||||
* We also need to set the value for LPC I/F Enables Register.
|
||||
*/
|
||||
pci_write_config8(dev, COM_DEC, 0x10);
|
||||
pci_write_config16(dev, LPC_EN, 0x300F);
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
/* Set the value for PCI command register. */
|
||||
pci_write_config16(dev, PCI_COMMAND, 0x000f);
|
||||
|
||||
i82801ax_enable_acpi(dev);
|
||||
/* IO APIC initialization. */
|
||||
i82801ax_enable_ioapic(dev);
|
||||
|
||||
i82801ax_enable_serial_irqs(dev);
|
||||
|
||||
/* Setup the PIRQ. */
|
||||
i82801ax_pirq_init(dev);
|
||||
|
||||
/* Setup power options. */
|
||||
i82801ax_power_options(dev);
|
||||
|
||||
/* Set the state of the GPIO lines. */
|
||||
gpio_init(dev);
|
||||
|
||||
/* Initialize the real time clock. */
|
||||
i82801ax_rtc_init(dev);
|
||||
|
||||
/* Route DMA. */
|
||||
i82801ax_lpc_route_dma(dev, 0xff);
|
||||
|
||||
/* Initialize ISA DMA. */
|
||||
isa_dma_init();
|
||||
|
||||
/* Setup decode ports and LPC I/F enables. */
|
||||
i82801ax_lpc_decode_en(dev);
|
||||
}
|
||||
|
||||
static void i82801ax_lpc_read_resources(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
||||
/* Get the normal PCI resources of this device. */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* Add an extra subtractive resource for both memory and I/O. */
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
res->base = 0;
|
||||
res->size = 0x1000;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
res->base = 0xff800000;
|
||||
res->size = 0x00800000; /* 8 MB for flash */
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
|
||||
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = IO_APIC_ADDR;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = i82801ax_lpc_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = scan_lpc_bus,
|
||||
.enable = i82801ax_enable,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_lpc __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2410,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_lpc __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2420,
|
||||
};
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2005 Tyan Computer
|
||||
* (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
{
|
||||
u16 reg16;
|
||||
|
||||
/* Clear possible errors. */
|
||||
reg16 = pci_read_config16(dev, PCI_STATUS);
|
||||
reg16 |= 0xf900;
|
||||
pci_write_config16(dev, PCI_STATUS, reg16);
|
||||
}
|
||||
|
||||
static struct device_operations pci_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pci_init,
|
||||
.scan_bus = pci_scan_bridge,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_pci __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2418,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_pci __pci_driver = {
|
||||
.ops = &pci_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x2428,
|
||||
};
|
||||
@@ -1,24 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <reset.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
void do_hard_reset(void)
|
||||
{
|
||||
/* Try rebooting through port 0xcf9. */
|
||||
outb((1 << 2) | (1 << 1), 0xcf9);
|
||||
}
|
||||
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/smbus.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <southbridge/intel/common/smbus.h>
|
||||
#include "i82801ax.h"
|
||||
|
||||
static int lsmbus_read_byte(struct device *dev, u8 address)
|
||||
{
|
||||
u16 device;
|
||||
struct resource *res;
|
||||
struct bus *pbus;
|
||||
|
||||
device = dev->path.i2c.device;
|
||||
pbus = get_pbus_smbus(dev);
|
||||
res = find_resource(pbus->dev, 0x20);
|
||||
|
||||
return do_smbus_read_byte(res->base, device, address);
|
||||
}
|
||||
|
||||
static struct smbus_bus_operations lops_smbus_bus = {
|
||||
.read_byte = lsmbus_read_byte,
|
||||
};
|
||||
|
||||
static const struct device_operations smbus_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = scan_smbus,
|
||||
.enable = i82801ax_enable,
|
||||
.ops_smbus_bus = &lops_smbus_bus,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_smb __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AA_SMB,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_smb __pci_driver = {
|
||||
.ops = &smbus_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AB_SMB,
|
||||
};
|
||||
@@ -1,49 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "i82801ax.h"
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
/* TODO: Any init needed? Some ports have it, others don't. */
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = usb_init,
|
||||
.scan_bus = 0,
|
||||
.enable = i82801ax_enable,
|
||||
};
|
||||
|
||||
/* 82801AA (ICH) */
|
||||
static const struct pci_driver i82801aa_usb1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AA_USB,
|
||||
};
|
||||
|
||||
/* 82801AB (ICH0) */
|
||||
static const struct pci_driver i82801ab_usb1 __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_82801AB_USB,
|
||||
};
|
||||
@@ -1,51 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2006 John Dufresne <jon.dufresne@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <watchdog.h>
|
||||
|
||||
/* TODO: I'm fairly sure the same functionality is provided elsewhere. */
|
||||
|
||||
void watchdog_off(void)
|
||||
{
|
||||
struct device *dev;
|
||||
unsigned long value, base;
|
||||
|
||||
/* Turn off the ICH5 watchdog. */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
|
||||
|
||||
/* Enable I/O space. */
|
||||
value = pci_read_config16(dev, 0x04);
|
||||
value |= (1 << 10);
|
||||
pci_write_config16(dev, 0x04, value);
|
||||
|
||||
/* Get TCO base. */
|
||||
base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
|
||||
|
||||
/* Disable the watchdog timer. */
|
||||
value = inw(base + 0x08);
|
||||
value |= 1 << 11;
|
||||
outw(value, base + 0x08);
|
||||
|
||||
/* Clear TCO timeout status. */
|
||||
outw(0x0008, base + 0x04);
|
||||
outw(0x0002, base + 0x06);
|
||||
|
||||
printk(BIOS_DEBUG, "ICH Watchdog disabled\n");
|
||||
}
|
||||
Reference in New Issue
Block a user