From 2214f27d92816e5bbdaf1624761f81ef5356f3d5 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Sat, 14 Nov 2020 20:13:22 -0700 Subject: [PATCH] Add rtd3 config for lemp10 m.2 slots Change-Id: I0d49ba23205801dbcca7fe420ed8e763e1e80514 --- src/mainboard/system76/lemp10/devicetree.cb | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb index b113718f8e..b88a95d1fd 100644 --- a/src/mainboard/system76/lemp10/devicetree.cb +++ b/src/mainboard/system76/lemp10/devicetree.cb @@ -235,7 +235,14 @@ chip soc/intel/tigerlake device pci 02.0 on end # Graphics device pci 04.0 on end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 - device pci 06.0 on end # PEG60 0x9A09 + device pci 06.0 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end # PEG60 0x9A09 device pci 07.0 on end # TBT_PCIe0 0x9A23 device pci 07.1 off end # TBT_PCIe1 0x9A25 device pci 07.2 off end # TBT_PCIe2 0x9A27 @@ -297,7 +304,14 @@ chip soc/intel/tigerlake device pci 1c.5 on end # RP6 0xA0BD device pci 1c.6 off end # RP7 0xA0BE device pci 1c.7 off end # RP8 0xA0BF - device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.0 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 device pci 1d.2 off end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3