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soc/intel/skylake: Avoid TOL_1V8 being set for GPP_F4 ~ GPP_F11

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According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.

BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear

Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kane Chen
2019-02-12 21:14:13 +08:00
committed by Patrick Georgi
parent 1ac2ad0fbe
commit 223ddc298a
3 changed files with 34 additions and 0 deletions
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15
src/soc/intel/skylake/gpio.c
View File

@@ -168,3 +168,18 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
*num = ARRAY_SIZE(routes);
return routes;
}
uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
int dw_reg, uint32_t reg_val)
{
if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
return reg_val;
/*
* For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4
* ~ GPP_F11.
*/
if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
return reg_val;
}