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mb/google/nissa/var/uldren: Add FW_CONFIG probe for fivr

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Uldren will support internal fivr in next phase and using fw_config to
decide the board with internal or external fivr.

BUG=b:287379760
BRANCH=firmware-nissa-15217.B
TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS
work normally.

Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
This commit is contained in:
Dtrain Hsu
2023-07-13 11:22:54 +08:00
committed by Felix Held
parent c364f42147
commit 22c616e6f5
2 changed files with 27 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/mainboard/google/brya/variants/uldren/overridetree.cb
View File

@@ -17,6 +17,10 @@ fw_config
option TOUCHSCREEN_WDT8752A 5 option TOUCHSCREEN_WDT8752A 5
option TOUCHSCREEN_GTCH7502 6 option TOUCHSCREEN_GTCH7502 6
end end
field EXT_VR 14 14
option EXT_VR_PRESENT 0
option EXT_VR_ABSENT 1
end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
@@ -91,21 +95,6 @@ chip soc/intel/alderlake
[PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci,
}" }"
# Configure external V1P05/Vnn/VnnSx Rails
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
.v1p05_voltage_mv = 1050,
.vnn_voltage_mv = 780,
.vnn_sx_voltage_mv = 1050,
.v1p05_icc_max_ma = 500,
.vnn_icc_max_ma = 500,
}"
register "tcc_offset" = "3" register "tcc_offset" = "3"
# Intel Common SoC Config # Intel Common SoC Config

23
src/mainboard/google/brya/variants/uldren/variant.c
View File

@@ -43,3 +43,26 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
ARRAY_SIZE(lte_disable_pads)); ARRAY_SIZE(lte_disable_pads));
} }
} }
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_PRESENT))) {
config->ext_fivr_settings.configure_ext_fivr = 1;
config->ext_fivr_settings.v1p05_enable_bitmap =
FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0;
config->ext_fivr_settings.vnn_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.vnn_sx_enable_bitmap =
FIVR_ENABLE_ALL_SX;
config->ext_fivr_settings.v1p05_supported_voltage_bitmap =
FIVR_VOLTAGE_NORMAL;
config->ext_fivr_settings.vnn_supported_voltage_bitmap =
FIVR_VOLTAGE_MIN_ACTIVE;
config->ext_fivr_settings.v1p05_voltage_mv = 1050;
config->ext_fivr_settings.vnn_voltage_mv = 780;
config->ext_fivr_settings.vnn_sx_voltage_mv = 1050;
config->ext_fivr_settings.v1p05_icc_max_ma = 500;
config->ext_fivr_settings.vnn_icc_max_ma = 500;
printk(BIOS_INFO, "Configured External FIVR\n");
}
}