riscv: add support for supervisor binary interface (SBI)

SBI is runtime service for OS. For an introduction, please refer to
https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md

Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Xiang Wang
2018-08-15 16:27:05 +08:00
committed by Patrick Georgi
parent 26f725efc2
commit 22e0c560bb
5 changed files with 187 additions and 1 deletions

View File

@@ -102,6 +102,14 @@ DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd)
DEFINE_MPRV_WRITE(mprv_write_long, long, sd)
DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd)
#if __riscv_xlen == 32
DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, lw)
DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sw)
#elif __riscv_xlen == 64
DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, ld)
DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sd)
#endif
#undef DEFINE_MPRV_READ_FLAGS
#undef DEFINE_MPRV_READ
#undef DEFINE_MPRV_READ_MXR