riscv: add support for supervisor binary interface (SBI)
SBI is runtime service for OS. For an introduction, please refer to https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md Change-Id: Ib6c1f21d2f085f02208305dc4e3a0f970d400c27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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committed by
Patrick Georgi
parent
26f725efc2
commit
22e0c560bb
@@ -102,6 +102,14 @@ DEFINE_MPRV_WRITE(mprv_write_u64, uint64_t, sd)
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DEFINE_MPRV_WRITE(mprv_write_long, long, sd)
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DEFINE_MPRV_WRITE(mprv_write_ulong, unsigned long, sd)
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#if __riscv_xlen == 32
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DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, lw)
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DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sw)
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#elif __riscv_xlen == 64
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DEFINE_MPRV_READ(mprv_read_uintptr_t, uintptr_t, ld)
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DEFINE_MPRV_READ(mprv_write_uintptr_t, uintptr_t, sd)
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#endif
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#undef DEFINE_MPRV_READ_FLAGS
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#undef DEFINE_MPRV_READ
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#undef DEFINE_MPRV_READ_MXR
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