From 22ebfff8123c05c845148ac69f2401f6e8ee6da7 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 25 Feb 2022 09:12:56 -0700 Subject: [PATCH] Change AMD FW offsets to support 32 MiB SPI chips Change-Id: Ie5b056c60186fe9d64d260d788b2ac19c1f5b481 --- util/amdfwtool/amdfwtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index d088179265..ee0e2232d5 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -346,7 +346,7 @@ typedef struct _context { uint32_t current; /* pointer within flash & proxy buffer */ } context; -#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1) +#define RUN_BASE(ctx) (0) #define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset)) #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current) #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))