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soc/intel/skylake: Clean up UART code

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Clean up and move UART related code under a single uart.c file.

Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Aamir Bohra
2017-12-04 16:24:21 +05:30
committed by Subrata Banik
parent 75c6f4aeb6
commit 230ada6d3c
4 changed files with 54 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/soc/intel/skylake/Makefile.inc
View File

@@ -14,21 +14,20 @@ bootblock-y += bootblock/cpu.c
bootblock-y += i2c.c bootblock-y += i2c.c
bootblock-y += bootblock/pch.c bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/report_platform.c
bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c
bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c
bootblock-y += gpio.c bootblock-y += gpio.c
bootblock-y += gspi.c bootblock-y += gspi.c
bootblock-y += pch.c bootblock-y += pch.c
bootblock-y += pmutil.c bootblock-y += pmutil.c
bootblock-y += spi.c bootblock-y += spi.c
bootblock-y += lpc.c bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c verstage-y += gspi.c
verstage-y += pch.c verstage-y += pch.c
verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
verstage-y += pmutil.c verstage-y += pmutil.c
verstage-y += i2c.c verstage-y += i2c.c
verstage-y += spi.c verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
romstage-y += gpio.c romstage-y += gpio.c
romstage-y += gspi.c romstage-y += gspi.c
@@ -41,7 +40,7 @@ romstage-y += pmc.c
romstage-y += pmutil.c romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += spi.c romstage-y += spi.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c romstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
@@ -69,8 +68,7 @@ ramstage-y += smmrelocate.c
ramstage-y += spi.c ramstage-y += spi.c
ramstage-y += systemagent.c ramstage-y += systemagent.c
ramstage-y += thermal.c ramstage-y += thermal.c
ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart.c
ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-y += vr_config.c ramstage-y += vr_config.c
smm-y += elog.c smm-y += elog.c
@@ -78,13 +76,12 @@ smm-y += gpio.c
smm-y += pch.c smm-y += pch.c
smm-y += pmutil.c smm-y += pmutil.c
smm-y += smihandler.c smm-y += smihandler.c
smm-$(CONFIG_UART_DEBUG) += uart_debug.c smm-$(CONFIG_UART_DEBUG) += uart.c
smm-y += uart.c
postcar-y += memmap.c postcar-y += memmap.c
postcar-$(CONFIG_UART_DEBUG) += uart_debug.c
postcar-y += gspi.c postcar-y += gspi.c
postcar-y += spi.c postcar-y += spi.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
# cpu_microcode_bins += ??? # cpu_microcode_bins += ???

57
src/soc/intel/skylake/bootblock/uart.c
View File

@@ -1,57 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
* Copyright (C) 2016 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/uart.h>
#include <device/pci_def.h>
#include <gpio.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h>
#include <soc/bootblock.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
void pch_uart_init(void)
{
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(PCH_DEV_UART2, base);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(base);
}
gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}

50
src/soc/intel/skylake/uart.c
View File

@@ -2,7 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation * Copyright (C) 2015-2017 Intel Corporation
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -15,11 +15,57 @@
*/ */
#include <cbmem.h> #include <cbmem.h>
#include <console/uart.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_def.h>
#include <gpio.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pcr.h>
#include <intelblocks/uart.h> #include <intelblocks/uart.h>
#include <soc/iomap.h> #include <soc/bootblock.h>
#include <soc/nvs.h> #include <soc/nvs.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* Serial IO UART controller legacy mode */
#define PCR_SERIAL_IO_GPPRVRW7 0x618
#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx))
/* UART2 pad configuration. Support RXD and TXD for now. */
static const struct pad_config uart2_pads[] = {
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
};
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM)
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
* is currently only supported. */
return UART_BASE_0_ADDR(idx);
}
#endif
void pch_uart_init(void)
{
uintptr_t base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
uart_common_init(PCH_DEV_UART2, base);
/* Put UART2 in byte access mode for 16550 compatibility */
if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) {
pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7,
PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE));
/*
* Dummy read after setting any of GPPRVRW7.
* Required for UART 16550 8-bit Legacy mode to become active
*/
lpss_clk_read(base);
}
gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
}
#if !ENV_SMM #if !ENV_SMM
void pch_uart_read_resources(struct device *dev) void pch_uart_read_resources(struct device *dev)

26
src/soc/intel/skylake/uart_debug.c
View File

@@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <console/uart.h>
#include <soc/iomap.h>
#include <soc/serialio.h>
uintptr_t uart_platform_base(int idx)
{
/* Same base address for all debug port usage. In reality UART2
* is currently only supported. */
return UART_BASE_0_ADDR(idx);
}