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sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block

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Drop the redundant cimx_util, remove the includes when appropriate and
replace the implementation with amdblocks/acpimmio where needed.

TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Michał Żygowski
2019-11-28 12:59:44 +01:00
committed by Patrick Georgi
parent 00517b687a
commit 2317b4f114
19 changed files with 46 additions and 146 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/southbridge/amd/cimx/Makefile.inc
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@@ -14,7 +14,3 @@
#
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c

51
src/southbridge/amd/cimx/cimx_util.c
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@@ -1,51 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci.h>
#include <arch/io.h>
#include "cimx_util.h"
static void pmio_write_index(u16 port_base, u8 reg, u8 value)
{
outb(reg, port_base);
outb(value, port_base + 1);
}
static u8 pmio_read_index(u16 port_base, u8 reg)
{
outb(reg, port_base);
return inb(port_base + 1);
}
void pm_iowrite(u8 reg, u8 value)
{
pmio_write_index(PM_INDEX, reg, value);
}
u8 pm_ioread(u8 reg)
{
return pmio_read_index(PM_INDEX, reg);
}
void pm2_iowrite(u8 reg, u8 value)
{
pmio_write_index(PM2_INDEX, reg, value);
}
u8 pm2_ioread(u8 reg)
{
return pmio_read_index(PM2_INDEX, reg);
}

37
src/southbridge/amd/cimx/cimx_util.h
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@@ -1,37 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2014 Sage Electronic Engineering, LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CIMX_UTIL_H
#define CIMX_UTIL_H
#include <stdint.h>
/* FCH index/data registers */
#define BIOSRAM_INDEX 0xcd4
#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
#define PCI_INTR_INDEX 0xc00
#define PCI_INTR_DATA 0xc01
void pm_iowrite(u8 reg, u8 value);
u8 pm_ioread(u8 reg);
void pm2_iowrite(u8 reg, u8 value);
u8 pm2_ioread(u8 reg);
#endif /* CIMX_UTIL_H */

3
src/southbridge/amd/cimx/sb800/Kconfig
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@@ -21,6 +21,9 @@ config SOUTHBRIDGE_AMD_CIMX_SB800
select AMD_SB_CIMX
select HAVE_CF9_RESET
select HAVE_CF9_RESET_PREPARE
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
if SOUTHBRIDGE_AMD_CIMX_SB800
config BOOTBLOCK_SOUTHBRIDGE_INIT

12
src/southbridge/amd/cimx/sb800/fan.c
View File

@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
#include <southbridge/amd/cimx/cimx_util.h>
#include <amdblocks/acpimmio.h>
#include <device/device.h>
#include <device/pci.h> /* device_operations */
#include <device/pci_ops.h>
@@ -31,27 +31,27 @@ void init_sb800_MANUAL_fans(struct device *dev)
/* Init Fan 0 */
if (sb_chip->fan0_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_iowrite(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);
pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]);
/* Init Fan 1 */
if (sb_chip->fan1_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_iowrite(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);
pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]);
/* Init Fan 2 */
if (sb_chip->fan2_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_iowrite(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);
pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]);
/* Init Fan 3 */
if (sb_chip->fan3_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_iowrite(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);
pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]);
/* Init Fan 4 */
if (sb_chip->fan4_enabled)
for (i = 0; i < FAN_REGISTER_COUNT; i++)
pm2_iowrite(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]);
}