split the one file, as the several printing functions will continue to grow
immensly when they know more systems / cpus / chipsets Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
committed by
Stefan Reinauer
Stefan Reinauer
parent
eb02f45e6f
commit
2319027d7e
199
util/inteltool/pcie.c
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199
util/inteltool/pcie.c
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <sys/mman.h>
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#include "inteltool.h"
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/*
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* Egress Port Root Complex MMIO configuration space
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*/
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int print_epbar(struct pci_dev *nb)
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{
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int i, size = (4 * 1024);
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volatile uint8_t *epbar;
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uint32_t epbar_phys;
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printf("\n============= EPBAR =============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82945GM:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This northbrigde does not have EPBAR.\n");
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return 1;
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default:
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printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) epbar_phys);
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if (epbar == MAP_FAILED) {
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perror("Error mapping EPBAR");
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exit(1);
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}
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printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(epbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
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}
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munmap((void *)epbar, size);
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return 0;
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}
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/*
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* MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
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*/
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int print_dmibar(struct pci_dev *nb)
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{
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int i, size = (4 * 1024);
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volatile uint8_t *dmibar;
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uint32_t dmibar_phys;
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printf("\n============= DMIBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82945GM:
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dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This northbrigde does not have DMIBAR.\n");
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return 1;
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default:
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printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
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fd_mem, (off_t) dmibar_phys);
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if (dmibar == MAP_FAILED) {
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perror("Error mapping DMIBAR");
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exit(1);
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}
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printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys);
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(dmibar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
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}
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munmap((void *)dmibar, size);
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return 0;
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}
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/*
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* PCIe MMIO configuration space
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*/
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int print_pciexbar(struct pci_dev *nb)
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{
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uint32_t pciexbar_reg;
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uint32_t pciexbar_phys;
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volatile uint8_t *pciexbar;
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int max_busses, devbase, i;
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int bus, dev, fn;
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printf("========= PCIEXBAR ========\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82945GM:
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pciexbar_reg = pci_read_long(nb, 0x48);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("Error: This northbrigde does not have PCIEXBAR.\n");
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return 1;
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default:
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printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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if (!(pciexbar_reg & (1 << 0))) {
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printf("PCIEXBAR register is disabled.\n");
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return 0;
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}
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
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max_busses = 256;
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break;
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case 1: // 128M
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pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
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max_busses = 128;
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break;
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case 2: // 64M
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pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
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max_busses = 64;
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break;
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default: // RSVD
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printf("Undefined address base. Bailing out.\n");
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return 1;
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}
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printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
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pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
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MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
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if (pciexbar == MAP_FAILED) {
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perror("Error mapping PCIEXBAR");
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exit(1);
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}
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for (bus = 0; bus < max_busses; bus++) {
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for (dev = 0; dev < 32; dev++) {
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for (fn = 0; fn < 8; fn++) {
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devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
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if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
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continue;
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/* This is a heuristics. Anyone got a better check? */
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if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
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(*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
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#if DEBUG
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printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
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#endif
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continue;
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}
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printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
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for (i = 0; i < 4096; i++) {
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if((i % 0x10) == 0)
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printf("\n%04x:", i);
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printf(" %02x", *(pciexbar+devbase+i));
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}
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printf("\n");
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}
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}
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}
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munmap((void *)pciexbar, (max_busses * 1024 * 1024));
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return 0;
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}
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