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riscv: add trampoline in MBR block to support boot mode 1

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Add "j pc + 0x0800" at the beginning of the MBR to jump to bootblock.

Tested on hardware:
boot mode 15: works as before
boot mode 1: jump to bootblock works, but bootblock needs to be modified to
move the stack to L2LIM. This will be in a separate commit.

Further changes are needed in the bootblock

Change-Id: I16e762d9f027346b124412f1f7ee6ff37f431d86
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This commit is contained in:
Philipp Hug
2018-07-07 15:54:37 +02:00
committed by Ronald G. Minnich
parent 2912e8e5dc
commit 2326a284ac
2 changed files with 14 additions and 2 deletions
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Documentation/mainboard/sifive/hifive-unleashed.md
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@@ -11,7 +11,7 @@ For general setup instructions, please refer to the [Getting Started Guide].
The following things are still missing from this coreboot port:
- Trampoline in the MBR block to support boot mode 1
- Support running romstage from flash (fix stack) to support boot mode 1
- CBMEM support
- FU540 clock configuration
- FU540 RAM init