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zero warnings days...

Browse Source 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-15 12:39:29 +00:00
committed by Stefan Reinauer
parent c30a6e859e
commit 23836e2345
48 changed files with 826 additions and 981 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/drivers/ati/ragexl/mach64_ct.c
View File

@ -1,4 +1,5 @@
#define DEBUG_PLL 0
#define PLL_CRTC_DECODE 0
/* FIXME: remove the FAIL definition */
#if 0
@ -123,9 +124,7 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
#if DEBUG_PLL==1
int pllmclk, pllsclk;
#endif
u32 q, x; /* x is a workaround for sparc64-linux-gcc */
x = x; /* x is a workaround for sparc64-linux-gcc */
u32 q;
pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;

2
src/drivers/ati/ragexl/xlinit.c
View File

@ -485,12 +485,12 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
static void ati_ragexl_init(device_t dev)
{
u32 chip_id;
u32 i;
int j;
u16 type;
u8 rev;
const char *chipname = NULL;
#if CONFIG_CONSOLE_BTEXT
u32 i;
const char *xtal;
#endif
int pll, mclk, xclk;

1
src/include/boot/tables.h
View File

@ -2,6 +2,7 @@
#define BOOT_TABLES_H
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
void lb_add_memory_range(struct lb_memory *mem,
uint32_t type, uint64_t start, uint64_t size);

7
src/mainboard/amd/dbm690t/mainboard.c
View File

@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \

8
src/mainboard/amd/mahogany/mainboard.c
View File

@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/coreboot_tables.h>
#include <../southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);

8
src/mainboard/amd/mahogany_fam10/mainboard.c
View File

@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/coreboot_tables.h>
#include <../southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);

8
src/mainboard/amd/pistachio/mainboard.c
View File

@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7475_ADDRESS 0x2E
@ -35,9 +34,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
#define ADT7475_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
#define ADT7475_write_byte(address, val) \

5
src/mainboard/amd/serengeti_cheetah/romstage.c
View File

@ -101,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
/* tyan does not want the default */

2
src/mainboard/asrock/939a785gmh/get_bus_conf.c
View File

@ -63,8 +63,6 @@ u32 sbdn_sb700;
static u32 get_bus_conf_done = 0;
void get_bus_conf(void);
void get_bus_conf(void)
{
u32 apicid_base;

8
src/mainboard/asrock/939a785gmh/mainboard.c
View File

@ -21,19 +21,15 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <arch/coreboot_tables.h>
#include <../southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/sb700.h>
#include "chip.h"
#define SMBUS_IO_BASE 0x6000
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
uint64_t uma_memory_base, uma_memory_size;
void set_pcie_dereset(void);

15
src/mainboard/asus/a8v-e_se/romstage.c
View File

@ -105,10 +105,11 @@ void soft_reset(void)
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/via/k8t890/k8t890_early_car.c"
@ -126,7 +127,7 @@ unsigned int get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
void sio_init(void)
static void sio_init(void)
{
u8 reg;
@ -171,17 +172,17 @@ void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
#endif
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
sio_init();
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

3
src/mainboard/asus/m2v-mx_se/mainboard.c
View File

@ -21,9 +21,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
#include <southbridge/via/k8t890/k8t890.h>
#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{

30
src/mainboard/asus/m2v-mx_se/romstage.c
View File

@ -70,10 +70,6 @@ unsigned int get_sbdn(unsigned bus);
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -83,18 +79,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
void activate_spd_rom(const struct mem_controller *ctrl)
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
@ -144,34 +142,21 @@ unsigned int get_sbdn(unsigned bus)
return (dev >> 15) & 0x1f;
}
void sio_init(void)
{
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
real_main(bist, cpu_init_detectedx);
}
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
#endif
};
unsigned bsp_apicid = 0;
int needs_reset = 0;
struct sys_info *sysinfo =
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
sio_init();
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
it8712f_enable_3vsbsw();
@ -234,7 +219,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* It's the time to set ctrl now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}

15
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -86,10 +86,6 @@
#include "southbridge/sis/sis966/sis966_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -105,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -165,12 +158,12 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
@ -275,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sis_init_stage1();
enable_smbus();
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID

22
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -84,10 +84,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -103,12 +99,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -132,8 +125,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -145,8 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
@ -166,15 +155,16 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif
};
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@ -289,8 +279,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID

9
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -107,16 +107,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
//#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
//first node
@ -212,8 +207,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
//setup_mp_resource_map();
uart_init();
/* Halt if there was a built in self test failure */

77
src/mainboard/intel/eagleheights/debug.c
View File

@ -38,7 +38,7 @@ static void print_reg(unsigned char index)
return;
}
static void xbus_en(void)
static inline void xbus_en(void)
{
/* select the XBUS function in the SIO */
outb(0x07, 0x2e);
@ -66,7 +66,7 @@ static void setup_func(unsigned char func)
return;
}
static void siodump(void)
static inline void siodump(void)
{
int i;
unsigned char data;
@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev)
print_debug_hex8((dev >> 8) & 7);
}
static void print_pci_devices(void)
static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@ -161,7 +161,7 @@ static void print_pci_devices(void)
}
}
static void dump_pci_device(unsigned dev)
static inline void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
@ -182,7 +182,7 @@ static void dump_pci_device(unsigned dev)
}
}
static void dump_bar14(unsigned dev)
static inline void dump_bar14(unsigned dev)
{
int i;
unsigned long bar;
@ -227,70 +227,7 @@ static void dump_pci_devices(void)
}
}
#if 0
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
print_debug("\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\n");
}
}
}
#endif
void dump_spd_registers(void)
static inline void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
@ -322,7 +259,7 @@ void dump_spd_registers(void)
}
}
void dump_ipmi_registers(void)
static inline void dump_ipmi_registers(void)
{
unsigned device;
device = 0x42;

6
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"

6
src/mainboard/iwill/dk8s2/romstage.c
View File

@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"

6
src/mainboard/iwill/dk8x/romstage.c
View File

@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
#include "lib/ramtest.c"
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"

5
src/mainboard/kontron/kt690/mainboard.c
View File

@ -21,8 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \

15
src/mainboard/msi/ms7260/romstage.c
View File

@ -83,7 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void) {}
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@ -93,10 +92,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@ -144,16 +144,17 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
// Node 1
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
#endif
};
struct sys_info *sysinfo =
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@ -252,8 +253,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
memreset_setup();
/* Do we need apci timer, tsc...., only debug need it for better output */
/* All AP stopped? */
// init_timer(); /* Need to use TMICT to synconize FID/VID. */

14
src/mainboard/msi/ms9185/romstage.c
View File

@ -71,9 +71,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -104,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
/* msi does not want the default */
@ -129,7 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define DIMM6 0x56
#define DIMM7 0x57
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -144,12 +137,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
//first node
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
//second node
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
#endif
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
@ -278,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID

9
src/mainboard/msi/ms9282/romstage.c
View File

@ -68,9 +68,6 @@
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@ -103,9 +100,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
/* msi does not want the default */
@ -228,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
memreset_setup();
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();

3
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
View File

@ -92,11 +92,9 @@ static unsigned get_hcid(unsigned i)
void get_bus_conf(void)
{
unsigned apicid_base;
struct mb_sysconf_t *m;
device_t dev;
int i, j;
if (get_bus_conf_done)
@ -160,5 +158,4 @@ void get_bus_conf(void)
#endif
m->apicid_mcp55 = apicid_base+0;
m->apicid_mcp55b = apicid_base+1;
}

11
src/mainboard/nvidia/l1_2pvv/romstage.c
View File

@ -83,10 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -274,8 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID

2
src/mainboard/olpc/btest/mainboard.c
View File

@ -69,7 +69,7 @@ static void init_dcon(void) {
write_bit(rev > 0 ? 1 : 0);
}
void
static void
init_cafe_irq(void){
const unsigned char slots_cafe[4] = {11, 0, 0, 0};

1
src/mainboard/sunw/ultra40/get_bus_conf.c
View File

@ -7,6 +7,7 @@
#include <cpu/amd/multicore.h>
#endif
#include <stdlib.h>
#include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables

1
src/mainboard/sunw/ultra40/irq_tables.c
View File

@ -9,6 +9,7 @@
#include <string.h>
#include <stdint.h>
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,

3
src/mainboard/sunw/ultra40/mptable.c
View File

@ -3,6 +3,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
@ -32,8 +33,6 @@ extern unsigned hcdn[];
extern unsigned sbdn3;
extern unsigned sbdnb;
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";

13
src/mainboard/supermicro/h8dme/romstage.c
View File

@ -77,10 +77,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -154,12 +150,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -175,8 +168,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -340,8 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus(); /* enable in sio_setup */
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID

15
src/mainboard/supermicro/h8dmr/romstage.c
View File

@ -80,10 +80,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -99,12 +95,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -120,8 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -263,8 +254,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// enable_smbus(); /* enable in sio_setup */
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
@ -272,6 +261,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

11
src/mainboard/technexion/tim5690/mainboard.c
View File

@ -21,8 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
@ -179,7 +178,7 @@ static void set_thermal_config(void)
}
/* Mainboard specific GPIO setup. */
void mb_gpio_init(u16 *iobase)
static void mb_gpio_init(u16 *iobase)
{
/* Init Super I/O GPIOs. */
it8712f_enter_conf();
@ -193,7 +192,7 @@ void mb_gpio_init(u16 *iobase)
}
/* The LCD's panel id seletion. */
void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
{
switch (num_id) {
case 0x1:
@ -226,9 +225,6 @@ void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
*************************************************/
static void tim5690_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
rs690_vbios_regs vbios_regs;
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
u8 port2;
@ -240,6 +236,7 @@ static void tim5690_enable(device_t dev)
/* The LCD's panel id seletion by switch. */
port2 = inb(gpio_base+1);
lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
/* No support TV */
vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
vgabios_init(&vbios_regs);

1
src/mainboard/technexion/tim5690/vgabios.c
View File

@ -36,6 +36,7 @@ static void vbios_fun_init(rs690_vbios_regs *vbios_regs)
vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
}
/* BIOS int15 function */
int tim5690_int15_handler(struct eregs *regs)
{

7
src/mainboard/technexion/tim8690/mainboard.c
View File

@ -21,12 +21,11 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <arch/coreboot_tables.h>
#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <../southbridge/amd/sb600/sb600.h>
#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
@ -36,8 +35,6 @@
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \

1
src/mainboard/tyan/s2735/romstage.c
View File

@ -15,7 +15,6 @@
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"

15
src/mainboard/tyan/s2912/romstage.c
View File

@ -83,10 +83,6 @@
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
}
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
@ -130,8 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@ -271,8 +262,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID
@ -280,6 +269,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}

5
src/mainboard/via/epia-m700/Makefile.inc
View File

@ -19,5 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
obj-y += wakeup.o
# This code is unused and should be replaced by the generic resume code
# completely. If anyone works on wakeup for this chipset/board, delete
# wakeup.c when you are done.
# obj-y += wakeup.o

23
src/mainboard/via/epia-m700/wakeup.c
View File

@ -19,6 +19,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* FIXME This code should be dropped and instead the generic resume code
* should be used.
*/
/* Parts of this code is taken from reboot.c from Linux. */
/*
@ -96,19 +100,6 @@ static unsigned char jump_to_wakeup[] = {
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
};
/*
* Switch to real mode and then execute the code
* specified by the code and length parameters.
* We assume that length will aways be less that 100!
*/
static unsigned char show31[6] = {
0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
};
static unsigned char show32[6] = {
0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
};
void acpi_jump_wake(u32 vector)
{
u32 dwEip;
@ -337,8 +328,6 @@ void acpi_jump_wake(u32 vector)
* Enable A20 gate (return -1 on failure)
*/
// #include "boot.h"
#define MAX_8042_LOOPS 100000
static int empty_8042(void)
@ -375,13 +364,9 @@ static int a20_test(int loops)
int ok = 0;
int saved, ctr;
// set_fs(0x0000);
// set_gs(0xffff);
saved = ctr = *((u32 *) A20_TEST_ADDR);
while (loops--) {
//wrfs32(++ctr, A20_TEST_ADDR);
*((u32 *) A20_TEST_ADDR) = ++ctr;

2
src/mainboard/via/epia-n/mainboard.c
View File

@ -23,8 +23,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <boot/tables.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include "chip.h"
#include "../../../southbridge/via/vt8237r/vt8237r.h"
int add_mainboard_resources(struct lb_memory *mem)
{

12
src/northbridge/amd/amdk8/raminit_f.c
View File

@ -718,12 +718,14 @@ static int is_dual_channel(const struct mem_controller *ctrl)
static int is_opteron(const struct mem_controller *ctrl)
{
/* Test to see if I am an Opteron.
* FIXME Testing dual channel capability is correct for now
* but a better test is probably required.
* m2 and s1g1 support dual channel too. but only support unbuffered dimm
/* Test to see if I am an Opteron. M2 and S1G1 support dual
* channel, too, but only support unbuffered DIMMs so we need a
* better test for Opterons.
* However, all code uses is_opteron() to find out whether to
* use dual channel, so if we really check for opteron here, we
* need to fix up all code using this function, too.
*/
#warning "FIXME implement a better test for opterons"
uint32_t nbcap;
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
return !!(nbcap & NBCAP_128Bit);

14
src/northbridge/intel/e7501/debug.c
View File

@ -13,7 +13,7 @@ static void print_debug_pci_dev(unsigned dev)
print_debug_hex8((dev >> 8) & 7);
}
static void print_pci_devices(void)
static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@ -58,7 +58,7 @@ static void dump_pci_device(unsigned dev)
print_debug("\n");
}
static void dump_pci_devices(void)
static inline void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@ -75,7 +75,7 @@ static void dump_pci_devices(void)
}
}
static void dump_pci_devices_on_bus(unsigned busn)
static inline void dump_pci_devices_on_bus(unsigned busn)
{
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
@ -92,7 +92,7 @@ static void dump_pci_devices_on_bus(unsigned busn)
}
}
static void dump_spd_registers(const struct mem_controller *ctrl)
static inline void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
print_debug("\n");
@ -174,7 +174,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
}
}
}
static void dump_smbus_registers(void)
static inline void dump_smbus_registers(void)
{
unsigned device;
print_debug("\n");
@ -215,7 +215,7 @@ static void dump_smbus_registers(void)
}
}
static void dump_io_resources(unsigned port)
static inline void dump_io_resources(unsigned port)
{
int i;
@ -249,7 +249,7 @@ static void dump_io_resources(unsigned port)
}
}
static void dump_mem(unsigned start, unsigned end)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");

393
src/northbridge/intel/e7501/raminit.c
View File

@ -64,7 +64,8 @@ static const uint32_t refresh_frequency[]= {
* [6] reserved -> 0
* [7] 64 clocks -> 4
*/
0, 2, 3, 1, 0, 0, 0, 4 };
0, 2, 3, 1, 0, 0, 0, 4
};
static const uint32_t refresh_rate_map[] = {
/* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
@ -81,8 +82,8 @@ static const uint32_t refresh_rate_map[] = {
*/
1, 7, 2, 1, 1, 3
};
#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
// SPD parameters that must match for dual-channel operation
static const uint8_t dual_channel_parameters[] = {
@ -453,7 +454,7 @@ static const uint32_t maybe_pull_updown_offset_table[] = {
/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
/* TABLES */
/**********************************************************************************/
#define SLOW_DOWN_IO inb(0x80);
#define SLOW_DOWN_IO inb(0x80)
//#define SLOW_DOWN_IO udelay(40);
/* Estimate that SLOW_DOWN_IO takes about 50&76us */
@ -463,17 +464,19 @@ static const uint32_t maybe_pull_updown_offset_table[] = {
static void do_delay(void)
{
int i;
for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
for (i = 0; i < 16; i++) {
SLOW_DOWN_IO;
}
#define DO_DELAY do_delay();
}
#define DO_DELAY do_delay()
#else
#define DO_DELAY \
udelay(200);
udelay(200)
#endif
#define EXTRA_DELAY DO_DELAY
/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
/* DELAY FUNCTIONS */
/**********************************************************************************/
@ -493,7 +496,8 @@ static void die_on_spd_error(int spd_return_value)
//
// NOTE: page size is the total number of data bits in a row.
//
static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
static struct dimm_size sdram_spd_get_page_size(uint16_t
dimm_socket_address)
{
uint16_t module_data_width;
int value;
@ -504,30 +508,38 @@ static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
// Side 1
value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
if (value < 0) goto hw_err;
if (value < 0)
goto hw_err;
pgsz.side1 = value & 0xf; // # columns in bank 1
/* Get the module data width and convert it to a power of two */
value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
if (value < 0)
goto hw_err;
module_data_width = (value & 0xff) << 8;
value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
if (value < 0)
goto hw_err;
module_data_width |= (value & 0xff);
pgsz.side1 += log2(module_data_width);
/* side two */
value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
if (value < 0) goto hw_err;
if (value < 0)
goto hw_err;
if (value > 2)
die("Bad SPD value\n");
if (value == 2) {
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
if (value < 0)
goto hw_err;
if ((value & 0xf0) != 0) {
// Asymmetric banks
pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
@ -542,7 +554,6 @@ hw_err:
return pgsz; // Never reached
}
//----------------------------------------------------------------------------------
// Function: sdram_spd_get_width
// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate
@ -558,7 +569,8 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
width.side1 = 0;
width.side2 = 0;
value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
value =
spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
die_on_spd_error(value);
width.side1 = value & 0x7f; // Mask off bank 2 flag
@ -567,7 +579,8 @@ static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
} else {
// If bank 2 exists, it's the same width as bank 1
value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
value =
spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
die_on_spd_error(value);
#ifdef ROMCC_IF_BUG_FIXED
@ -623,7 +636,9 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
sz.side2 += value; // Symmetric
}
value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM);
value =
spd_read_byte(dimm_socket_address,
SPD_NUM_BANKS_PER_SDRAM);
die_on_spd_error(value);
value = log2(value);
@ -635,6 +650,7 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
return sz;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
//----------------------------------------------------------------------------------
// Function: are_spd_values_equal
// Parameters: spd_byte_number -
@ -643,7 +659,8 @@ static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
// SPD parameter; 0 if the values differed or an error occurred.
// Description: Determine whether two DIMMs have the same value for a SPD parameter.
//
static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address,
static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
uint16_t dimm0_address,
uint16_t dimm1_address)
{
uint8_t bEqual = 0;
@ -651,11 +668,13 @@ static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_addr
int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value))
if ((dimm0_value >= 0) && (dimm1_value >= 0)
&& (dimm0_value == dimm1_value))
bEqual = 1;
return bEqual;
}
#endif
//----------------------------------------------------------------------------------
// Function: spd_get_supported_dimms
@ -691,29 +710,35 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
uint16_t channel0_dimm = ctrl->channel0[i];
uint16_t channel1_dimm = ctrl->channel1[i];
uint8_t bDualChannel = 1;
#ifdef VALIDATE_DIMM_COMPATIBILITY
struct dimm_size page_size;
struct dimm_size sdram_width;
#endif
int spd_value;
int j;
if (channel0_dimm == 0)
continue; // No such socket on this mainboard
if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR)
if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
SPD_MEMORY_TYPE_SDRAM_DDR)
continue;
#ifdef VALIDATE_DIMM_COMPATIBILITY
if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2)
if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
SPD_VOLTAGE_SSTL2)
continue; // Unsupported voltage
// E7501 does not support unregistered DIMMs
spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
spd_value =
spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
continue;
// Must support burst = 4 for dual-channel operation on E7501
// NOTE: for single-channel, burst = 8 is required
spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS);
spd_value =
spd_read_byte(channel0_dimm,
SPD_SUPPORTED_BURST_LENGTHS);
if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
continue;
@ -730,10 +755,10 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// If DIMM is double-sided, verify side2 page size
if (page_size.side2 != 0) {
if ((page_size.side2 < 15) || (page_size.side2 > 18))
if ((page_size.side2 < 15)
|| (page_size.side2 > 18))
continue;
}
// Validate SDRAM width
// The E7501 only supports x4 and x8 devices
@ -742,7 +767,8 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// If DIMM is double-sided, verify side2 width
if (sdram_width.side2 != 0) {
if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8))
if ((sdram_width.side2 != 4)
&& (sdram_width.side2 != 8))
continue;
}
#endif
@ -752,20 +778,25 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
// NOTE: unpopulated DIMMs cause read to fail
spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
spd_value =
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS);
spd_value =
spd_read_byte(channel1_dimm,
SPD_SUPPORTED_BURST_LENGTHS);
if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
continue;
int j;
for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) {
if (!are_spd_values_equal
(dual_channel_parameters[j], channel0_dimm,
channel1_dimm)) {
bDualChannel = 0;
break;
@ -778,8 +809,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
if (bDualChannel) {
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
}
else
} else
print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
@ -855,12 +885,12 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
} else
ASSERT(jedec_mode_bits == 0);
dimm_start_64M_multiple = 0;
for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
uint8_t dimm_end_64M_multiple =
pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i);
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
// This code assumes DRAM row boundaries are all set below 4 GB
@ -869,15 +899,18 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// NOTE: 2^26 == 64 MB
uint32_t dimm_start_address = dimm_start_64M_multiple << 26;
uint32_t dimm_start_address =
dimm_start_64M_multiple << 26;
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
RAM_DEBUG_MESSAGE("\n");
read32(dimm_start_address + e7501_mode_bits);
// Set the start of the next DIMM
dimm_start_64M_multiple = dimm_end_64M_multiple;
dimm_start_64M_multiple =
dimm_end_64M_multiple;
}
}
}
@ -895,7 +928,8 @@ static void set_ram_mode(uint16_t jedec_mode_bits)
{
ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
uint32_t dram_cas_latency =
pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
switch (dram_cas_latency) {
case DRT_CAS_2_5:
@ -930,10 +964,7 @@ static void set_ram_mode(uint16_t jedec_mode_bits)
// Description: Configure the E7501's DRAM Row Boundary registers for the memory
// present in the specified DIMM.
//
static uint8_t configure_dimm_row_boundaries(
struct dimm_size dimm_log2_num_bits,
uint8_t total_dram_64M_multiple,
unsigned dimm_index)
static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
{
int i;
@ -941,7 +972,8 @@ static uint8_t configure_dimm_row_boundaries(
// DIMM sides must be at least 32 MB
ASSERT(dimm_log2_num_bits.side1 >= 28);
ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28));
ASSERT((dimm_log2_num_bits.side2 == 0)
|| (dimm_log2_num_bits.side2 >= 28));
// In dual-channel mode, we are called only once for each pair of DIMMs.
// Each time we process twice the capacity of a single DIMM.
@ -959,22 +991,27 @@ static uint8_t configure_dimm_row_boundaries(
total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
// Configure the boundary address for the row on side 1
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple);
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1),
total_dram_64M_multiple);
// If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
// (as a multiple of 64 MB) to the total capacity of the system
if (dimm_log2_num_bits.side2 >= 29)
total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29));
total_dram_64M_multiple +=
(1 << (dimm_log2_num_bits.side2 - 29));
// Configure the boundary address for the row (if any) on side 2
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple);
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1),
total_dram_64M_multiple);
// Update boundaries for rows subsequent to these.
// These settings will be overridden by a subsequent call if a populated physical slot exists
for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple);
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple);
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1),
total_dram_64M_multiple);
pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1),
total_dram_64M_multiple);
}
return total_dram_64M_multiple;
@ -992,8 +1029,8 @@ static uint8_t configure_dimm_row_boundaries(
// don't waste DRAM that ordinarily would lie behind addresses
// reserved for memory-mapped I/O.
//
static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
uint8_t dimm_mask)
static void configure_e7501_ram_addresses(const struct mem_controller
*ctrl, uint8_t dimm_mask)
{
int i;
uint8_t total_dram_64M_multiple = 0;
@ -1022,7 +1059,8 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
if (sz.side1 == 0)
die("Bad SPD value\n");
total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
total_dram_64M_multiple =
configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
}
// Configure the Top Of Low Memory (TOLM) in the E7501
@ -1051,12 +1089,15 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
// Round up to 128MB granularity
// SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1;
uint8_t total_dram_128M_multiple =
(total_dram_64M_multiple + 1) >> 1;
// Convert to high 16 bits of address
uint16_t top_of_low_memory = total_dram_128M_multiple << 11;
uint16_t top_of_low_memory =
total_dram_128M_multiple << 11;
pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory);
pci_write_config16(PCI_DEV(0, 0, 0), TOLM,
top_of_low_memory);
} else {
@ -1078,11 +1119,14 @@ static void configure_e7501_ram_addresses(const struct mem_controller *ctrl,
if (total_dram_64M_multiple < 0x40) {
remap_base = 0x40; // 0x100000000
remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1;
remap_limit =
0x40 + (total_dram_64M_multiple - 0x30) - 1;
}
pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base);
pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit);
pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE,
remap_base);
pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT,
remap_limit);
}
}
@ -1112,8 +1156,8 @@ static void initialize_ecc(void)
// Wait for scrub cycle to complete
do {
byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
byte =
pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS);
} while ((byte & 0x08) == 0);
pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc);
@ -1144,7 +1188,8 @@ static void initialize_ecc(void)
// latency, which is assumed to have been programmed already), based
// on the parameters of the various installed DIMMs.
//
static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask)
static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
uint8_t dimm_mask)
{
int i;
uint32_t dram_timing;
@ -1152,15 +1197,16 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8
uint8_t slowest_row_precharge = 0;
uint8_t slowest_ras_cas_delay = 0;
uint8_t slowest_active_to_precharge_delay = 0;
uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
uint32_t current_cas_latency =
pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK;
// CAS# latency must be programmed beforehand
ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5));
ASSERT((current_cas_latency == DRT_CAS_2_0)
|| (current_cas_latency == DRT_CAS_2_5));
// Each timing parameter is determined by the slowest DIMM
for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
uint16_t dimm_socket_address;
if (!(dimm_mask & (1 << i)))
@ -1169,20 +1215,30 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8
if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
dimm_socket_address = ctrl->channel0[i];
else
dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
dimm_socket_address =
ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_MIN_ROW_PRECHARGE_TIME);
if (value < 0)
goto hw_err;
if (value > slowest_row_precharge)
slowest_row_precharge = value;
value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY);
if(value < 0 ) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_MIN_RAS_TO_CAS_DELAY);
if (value < 0)
goto hw_err;
if (value > slowest_ras_cas_delay)
slowest_ras_cas_delay = value;
value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if(value < 0 ) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
if (value < 0)
goto hw_err;
if (value > slowest_active_to_precharge_delay)
slowest_active_to_precharge_delay = value;
}
@ -1230,7 +1286,6 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8
else
dram_timing |= (2 << 9); // < 38 ns: 5 clocks
/* Trd */
/* Set to a 7 clock read delay. This is for 133Mhz
@ -1269,7 +1324,8 @@ hw_err:
// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs
// have in common, and program the E7501 to use it.
//
static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask)
static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
uint8_t dimm_mask)
{
int i;
int value;
@ -1279,7 +1335,8 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
// CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
// NOTE: E7501 supports only 2.0 and 2.5
uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
uint32_t system_compatible_cas_latencies =
SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
uint32_t current_cas_latency;
uint32_t dimm_compatible_cas_latencies;
@ -1293,18 +1350,25 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
dimm_socket_address = ctrl->channel0[i];
else
dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
dimm_socket_address =
ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_ACCEPTABLE_CAS_LATENCIES);
if (value < 0)
goto hw_err;
dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
// Can we support the highest CAS# latency?
value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (value < 0) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (value < 0)
goto hw_err;
// NOTE: At 133 MHz, 1 clock == 7.52 ns
if (value > 0x75) {
@ -1312,28 +1376,34 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
// Remove it from the bitmask of those supported by the DIMM that are compatible
dimm_compatible_cas_latencies &= ~current_cas_latency;
}
// Can we support the next-highest CAS# latency (max - 0.5)?
current_cas_latency >>= 1;
if (current_cas_latency != 0) {
value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND);
if(value < 0 ) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_SDRAM_CYCLE_TIME_2ND);
if (value < 0)
goto hw_err;
if (value > 0x75)
dimm_compatible_cas_latencies &= ~current_cas_latency;
dimm_compatible_cas_latencies &=
~current_cas_latency;
}
// Can we support the next-highest CAS# latency (max - 1.0)?
current_cas_latency >>= 1;
if (current_cas_latency != 0) {
value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD);
if(value < 0 ) goto hw_err;
value =
spd_read_byte(dimm_socket_address,
SPD_SDRAM_CYCLE_TIME_3RD);
if (value < 0)
goto hw_err;
if (value > 0x75)
dimm_compatible_cas_latencies &= ~current_cas_latency;
dimm_compatible_cas_latencies &=
~current_cas_latency;
}
// Restrict the system to CAS# latencies compatible with this DIMM
system_compatible_cas_latencies &= dimm_compatible_cas_latencies;
system_compatible_cas_latencies &=
dimm_compatible_cas_latencies;
/* go to the next DIMM */
}
@ -1345,34 +1415,35 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT);
dram_timing &= ~(DRT_CAS_MASK);
maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
maybe_dram_read_timing =
pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL);
maybe_dram_read_timing &= 0xF00C;
if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
dram_timing |= DRT_CAS_2_0;
maybe_dram_read_timing |= 0xBB1;
}
else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
} else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA);
uint32_t dram_row_attributes =
pci_read_config32(PCI_DEV(0, 0, 0), DRA);
dram_timing |= DRT_CAS_2_5;
// At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
// different value if all DIMM slots are populated
if ((dram_row_attributes & 0xff) && (dram_row_attributes & 0xff00) &&
(dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) {
if ((dram_row_attributes & 0xff)
&& (dram_row_attributes & 0xff00)
&& (dram_row_attributes & 0xff0000)
&& (dram_row_attributes & 0xff000000)) {
// All slots populated
maybe_dram_read_timing |= 0x0882;
}
else {
} else {
// Some unpopulated slots
maybe_dram_read_timing |= 0x0662;
}
}
else
} else
die("No CAS# latencies compatible with all DIMMs!!\n");
pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing);
@ -1387,8 +1458,8 @@ static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8
pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword);
pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing);
pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL,
maybe_dram_read_timing);
dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */
dword &= ~(1 << 26);
@ -1411,13 +1482,15 @@ hw_err:
// than required by the "most needy" DIMM. Also disable ECC if any
// of the DIMMs don't support it.
//
static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl,
static void configure_e7501_dram_controller_mode(const struct
mem_controller *ctrl,
uint8_t dimm_mask)
{
int i;
// Initial settings
uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
uint32_t controller_mode =
pci_read_config32(PCI_DEV(0, 0, 0), DRC);
uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
// Code below assumes that most aggressive settings are in
@ -1447,12 +1520,16 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
dimm_socket_address = ctrl->channel0[i];
else
dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
dimm_socket_address =
ctrl->channel1[i -
MAX_DIMM_SOCKETS_PER_CHANNEL];
// Disable ECC mode if any one of the DIMMs does not support ECC
// SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE);
value =
spd_read_byte(dimm_socket_address,
SPD_DIMM_CONFIG_TYPE);
die_on_spd_error(value);
if (value != ERROR_SCHEME_ECC) {
controller_mode &= ~(3 << 20);
@ -1465,17 +1542,16 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
print_err("unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
print_err("unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
// update the system setting
if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode])
if (refresh_frequency[dimm_refresh_mode] >
refresh_frequency[system_refresh_mode])
system_refresh_mode = dimm_refresh_mode;
#ifdef SUSPICIOUS_LOOKING_CODE
@ -1485,7 +1561,9 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
// Switch to 2 clocks for address/command if required by any one of the DIMMs
// NOTE: At 133 MHz, 1 clock == 7.52 ns
value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
value =
spd_read_byte(dimm_socket_address,
SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
die_on_spd_error(value);
if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */
@ -1513,8 +1591,8 @@ static void configure_e7501_dram_controller_mode(const struct mem_controller *ct
// the width of the SDRAM chips on each DIMM side (x4 or x8) and
// the page size of each DIMM side (4, 8, 16, or 32 KB).
//
static void configure_e7501_row_attributes(const struct mem_controller *ctrl,
uint8_t dimm_mask)
static void configure_e7501_row_attributes(const struct mem_controller
*ctrl, uint8_t dimm_mask)
{
int i;
uint32_t row_attributes = 0;
@ -1582,7 +1660,6 @@ static void enable_e7501_clocks(uint8_t dimm_mask)
pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable);
}
/*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/
/* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */
/**********************************************************************************/
@ -1639,11 +1716,13 @@ static void ram_set_d0f0_regs(void)
// Again, not strictly an error, but flagged as a potential bug
ASSERT((bits_to_mask & bits_to_set) == 0);
register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
register_value =
pci_read_config32(PCI_DEV(0, 0, 0), register_offset);
register_value &= bits_to_mask;
register_value |= bits_to_set;
pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value);
pci_write_config32(PCI_DEV(0, 0, 0), register_offset,
register_value);
}
}
@ -1654,7 +1733,7 @@ static void ram_set_d0f0_regs(void)
// Return Value: None
// Description: Copy 64 bytes from one location to another.
//
static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr)
static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
@ -1687,7 +1766,6 @@ static void ram_set_rcomp_regs(void)
dword |= (1 << 22);
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
// Set the RCOMP MMIO base address
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
@ -1696,7 +1774,6 @@ static void ram_set_rcomp_regs(void)
dword |= (1 << 9);
write32(RCOMP_MMIO + MAYBE_SMRCTL, dword);
/* Begin to write the RCOMP registers */
// Set CMD and DQ/DQS strength to 2x (?)
@ -1712,7 +1789,6 @@ static void ram_set_rcomp_regs(void)
// NOTE: some factory BIOS set 0x9088 here. Seems to work either way.
write16(RCOMP_MMIO + 0x40, 0);
// Set RCVEnOut# strength to 2x (?)
maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8;
maybe_strength_control |= 4;
@ -1747,7 +1823,6 @@ static void ram_set_rcomp_regs(void)
write8(RCOMP_MMIO + 0x2c, 0xff);
// Set the digital filter length to 8 (?)
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
@ -1796,7 +1871,8 @@ static void ram_set_rcomp_regs(void)
// then enable refresh and initialize ECC and memory to zero.
// Upon exit, SDRAM is up and running.
//
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
static void sdram_enable(int controllers,
const struct mem_controller *ctrl)
{
uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD);
uint32_t dram_controller_mode;
@ -1809,77 +1885,76 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
RAM_DEBUG_MESSAGE("Ram Enable 2\n");
/* A 200us delay is needed */
DO_DELAY
EXTRA_DELAY
DO_DELAY; EXTRA_DELAY;
/* 3. Apply NOP */
RAM_DEBUG_MESSAGE("Ram Enable 3\n");
do_ram_command(RAM_COMMAND_NOP, 0);
EXTRA_DELAY
EXTRA_DELAY;
/* 4 Precharge all */
RAM_DEBUG_MESSAGE("Ram Enable 4\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
EXTRA_DELAY;
/* wait until the all banks idle state... */
/* 5. Issue EMRS to enable DLL */
RAM_DEBUG_MESSAGE("Ram Enable 5\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
EXTRA_DELAY
do_ram_command(RAM_COMMAND_EMRS,
SDRAM_EXTMODE_DLL_ENABLE |
SDRAM_EXTMODE_DRIVE_NORMAL);
EXTRA_DELAY;
/* 6. Reset DLL */
RAM_DEBUG_MESSAGE("Ram Enable 6\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
EXTRA_DELAY
EXTRA_DELAY;
/* Ensure a 200us delay between the DLL reset in step 6 and the final
* mode register set in step 9.
* Infineon needs this before any other command is sent to the ram.
*/
DO_DELAY
EXTRA_DELAY
DO_DELAY; EXTRA_DELAY;
/* 7 Precharge all */
RAM_DEBUG_MESSAGE("Ram Enable 7\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
EXTRA_DELAY
EXTRA_DELAY;
/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
RAM_DEBUG_MESSAGE("Ram Enable 8\n");
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
/* And for good luck 6 more CBRs */
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
do_ram_command(RAM_COMMAND_CBR, 0);
EXTRA_DELAY
EXTRA_DELAY;
/* 9 mode register set */
RAM_DEBUG_MESSAGE("Ram Enable 9\n");
set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
EXTRA_DELAY
EXTRA_DELAY;
/* 10 DDR Receive FIFO RE-Sync */
RAM_DEBUG_MESSAGE("Ram Enable 10\n");
RAM_RESET_DDR_PTR();
EXTRA_DELAY
EXTRA_DELAY;
/* 11 normal operation */
RAM_DEBUG_MESSAGE("Ram Enable 11\n");
do_ram_command(RAM_COMMAND_NORMAL, 0);
EXTRA_DELAY
EXTRA_DELAY;
// Reconfigure the row boundaries and Top of Low Memory
// to match the true size of the DIMMs
@ -1889,8 +1964,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC);
dram_controller_mode |= (1 << 29);
pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode);
EXTRA_DELAY
EXTRA_DELAY;
initialize_ecc();
dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */
@ -1899,8 +1973,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
// verify_ram();
}
//----------------------------------------------------------------------------------
@ -1934,19 +2006,20 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
RAM_RESET_DDR_PTR();
configure_e7501_dram_timing(ctrl, dimm_mask);
DO_DELAY
DO_DELAY;
RAM_DEBUG_MESSAGE("done\n");
}
// NOTE: configure_e7501_ram_addresses() is NOT called here.
// We want to keep the default 64 MB/row mapping until sdram_enable() is called,
// even though the default mapping is almost certainly incorrect.
// The default mapping makes it easy to initialize all of the DIMMs
// even if the total system memory is > 4 GB.
//
// Save the dimm_mask for when sdram_enable is called, so it can call
// configure_e7501_ram_addresses() without having to regenerate the bitmask
// of usable DIMMs.
/* NOTE: configure_e7501_ram_addresses() is NOT called here.
* We want to keep the default 64 MB/row mapping until sdram_enable() is called,
* even though the default mapping is almost certainly incorrect.
* The default mapping makes it easy to initialize all of the DIMMs
* even if the total system memory is > 4 GB.
*
* Save the dimm_mask for when sdram_enable is called, so it can call
* configure_e7501_ram_addresses() without having to regenerate the bitmask
* of usable DIMMs.
*/
pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask);
}

3
src/northbridge/intel/e7501/raminit.h
View File

@ -15,5 +15,8 @@ struct mem_controller {
uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
};
#ifndef __ROMCC__
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
#endif
#endif /* RAMINIT_H */

1
src/northbridge/intel/i82830/northbridge.c
View File

@ -29,7 +29,6 @@
#include <string.h>
#include <bitops.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
#include "chip.h"
#include "i82830.h"

1
src/northbridge/intel/i945/northbridge.c
View File

@ -31,7 +31,6 @@
#include <boot/tables.h>
#include "chip.h"
#include "i945.h"
#include <arch/coreboot_tables.h>
static int get_pcie_bar(u32 *base, u32 *len)
{

3
src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
View File

@ -29,6 +29,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#ifdef UNUSED_CODE
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
@ -126,4 +127,4 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
print_debug("SMBUS Block complete\n");
return 0;
}
#endif

36
src/southbridge/via/vt8235/vt8235.c
View File

@ -7,18 +7,9 @@
#include <pc80/i8259.h>
#include "chip.h"
/*
* Base VT8235.
*/
void hard_reset(void)
{
printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n");
}
static void keyboard_on(struct device *dev)
{
unsigned char regval;
u8 regval;
regval = pci_read_config8(dev, 0x51);
regval |= 0x05;
@ -28,6 +19,7 @@ static void keyboard_on(struct device *dev)
pc_keyboard_init(0);
}
#ifdef UNUSED_CODE
void dump_south(device_t dev0)
{
int i,j;
@ -43,33 +35,37 @@ void dump_south(device_t dev0)
void set_led(void)
{
// set power led to steady now that lxbios has virtually done its job
// set power led to steady now that coreboot has virtually done its job
device_t dev;
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
pci_write_config8(dev, 0x94, 0xb0);
}
#endif
static void vt8235_enable(struct device *dev)
{
unsigned char regval;
unsigned short vendor,model;
u8 regval;
u16 vendor,model;
vendor = pci_read_config16(dev,0);
model = pci_read_config16(dev,0x2);
printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
/* if this is not the southbridge itself just return */
/* this is necessary because USB devices are slot 10, whereas this device is slot 11
therefore usb devices get called first during the bus scan */
/* If this is not the southbridge itself just return.
* This is necessary because USB devices are slot 10, whereas this
* device is slot 11 therefore usb devices get called first during
* the bus scan. We don't want to wait until we could do dev->init
* because that's too late.
*/
if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
return;
printk(BIOS_DEBUG, "Initialising Devices\n");
setup_i8259(); // make sure interupt controller is configured before keyboard init
/* make sure interupt controller is configured before keyboard init */
setup_i8259();
/* enable RTC and ethernet */
regval = pci_read_config8(dev, 0x51);
@ -79,7 +75,9 @@ static void vt8235_enable(struct device *dev)
/* turn on keyboard */
keyboard_on(dev);
/* enable USB 1.1 & USB 2.0 -redundant really since we've already been there - see note above*/
/* enable USB 1.1 & USB 2.0 - redundant really since we've
* already been there - see note above
*/
regval = pci_read_config8(dev, 0x50);
regval &= ~(0x36);
pci_write_config8(dev, 0x50, regval);