LiPPERT FrontRunner-AF [2/2]: actually implement mainboard support
Step 2: change the Persimmon code to adapt it to the new board's hardware.
The FrontRunner-AF is a PC/104+ form factor embedded board:
- AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU
- DDR3 SO-DIMM socket (1.5 or 1.35V)
- VGA and LVDS (via Analogix ANX3110)
- AMD A55E (Hudson-E1) southbridge
- 6x USB 2.0
- 1x SATA, 1x CFast socket
- HD Audio (via Realtek ALC886)
- PCI and ISA (via ITE IT8888)
- NEC uPD78F0532 microcontroller on I2C ("SEMA")
- Intel I210 GbE (on APU PCIe x1)
- SMSC SCH3112 SIO
- PS/2
- 2x RS232/485
- 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS)
http://www.adlinktech.com/PD/web/PD_detail.php?pid=1131
Change-Id: Id55f89d224ad669b351c36128b12299802b721ba
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2553
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jens Rottmann
committed by
Stefan Reinauer
Stefan Reinauer
parent
73d4965be9
commit
23d13b1d45
@@ -17,6 +17,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@@ -29,6 +30,109 @@
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#include <cpu/amd/agesa/s3_resume.h>
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#include <cpu/amd/mtrr.h>
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#include "SBPLATFORM.h"
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#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
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/* Init SIO GPIOs. */
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#define SIO_RUNTIME_BASE 0x0E00
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static const u16 sio_init_table[] = { // hi=offset, lo=value
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0x4BA0, // GP1x: COM1/2 control = RS232, no term, max 115200
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0x2300, // GP10: COM1 termination = push/pull output
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0x2400, // GP11: COM2 termination = push/pull output
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0x2500, // GP12: COM1 RS485 mode = push/pull output
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0x2600, // GP13: COM2 RS485 mode = push/pull output
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0x2700, // GP14: COM1 speed A = push/pull output
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0x2900, // GP15: COM1 speed B = push/pull output
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0x2A00, // GP16: COM2 speed A = push/pull output
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0x2B00, // GP17: COM2 speed B = push/pull output
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0x3904, // GP36 = KBDRST# function
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0x4E74, // GP4x: Ethernet enable = on
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0x6E84, // GP44: Ethernet enable = open drain output
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// GP5x = COM2 function instead of GPIO
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0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
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0x470C, // GP60 = WDT function
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0x5E00, // LED2: Live LED = off
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0x4884, // GP61: Live LED = LED2 function
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0x5038, // GP6x: USB power = 3x on
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0x5580, // GP63: USB power 0/1 = open drain output
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0x5680, // GP64: USB power 2/3 = open drain output
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0x5780, // GP65: USB power 4/5 = open drain output
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};
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/* Write data block to slave on SMBUS0. */
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#define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0)
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#define SMB0_CONTROL ((SMBUS0_BASE_ADDRESS) + 2)
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#define SMB0_HOSTCMD ((SMBUS0_BASE_ADDRESS) + 3)
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#define SMB0_ADDRESS ((SMBUS0_BASE_ADDRESS) + 4)
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#define SMB0_DATA0 ((SMBUS0_BASE_ADDRESS) + 5)
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#define SMB0_BLOCKDATA ((SMBUS0_BASE_ADDRESS) + 7)
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static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data)
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{
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__outbyte(SMB0_STATUS, 0x1E); // clear error status
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__outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out
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__outbyte(SMB0_HOSTCMD, command); // or destination offset
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__outbyte(SMB0_DATA0, length); // sent before data
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__inbyte(SMB0_CONTROL); // reset block data array
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while (length--)
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__outbyte(SMB0_BLOCKDATA, *(data++));
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__outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ
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while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors
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return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors
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}
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static void init(struct device *dev)
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{
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int i;
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printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__);
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/* Init Hudson GPIOs. */
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printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE);
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FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
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FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
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FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
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FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
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FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
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FCH_IOMUX( 57) = 1;
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FCH_GPIO ( 57) = 0x28;
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FCH_IOMUX( 58) = 1;
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FCH_GPIO ( 58) = 0x28;
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FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
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FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
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FCH_IOMUX( 61) = 2; // default to inputs with int. PU
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FCH_IOMUX( 62) = 2;
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FCH_IOMUX(187) = 2;
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FCH_IOMUX(188) = 2;
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FCH_IOMUX(189) = 1;
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FCH_IOMUX(190) = 1;
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FCH_IOMUX(191) = 1;
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FCH_IOMUX(192) = 1;
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if (!fch_gpio_state(197)) // just in case anyone cares
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printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n");
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printk(BIOS_INFO, "Board revision ID: %u\n",
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fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
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/* Init SIO GPIOs. */
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printk(BIOS_DEBUG, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE);
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for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) {
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u16 val = sio_init_table[i];
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outb((u8)val, SIO_RUNTIME_BASE + (val >> 8));
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}
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/* Notify the SMC we're alive and kicking, or after a while it will
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* effect a power cycle and switch to the alternate BIOS chip.
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* Should be done as late as possible. */
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printk(BIOS_INFO, "Sending BIOS alive message\n");
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const u8 i_am_alive[] = { 0x03 };
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if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive)))
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printk(BIOS_ERR, "smb_write_blk failed: %d\n", i);
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printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__);
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}
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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@@ -56,6 +160,7 @@ void set_pcie_dereset(void)
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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dev->ops->init = init;
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/*
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* The mainboard is the first place that we get control in ramstage. Check
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@@ -65,10 +170,10 @@ static void mainboard_enable(device_t dev)
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acpi_slp_type = acpi_get_sleep_type();
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#endif
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/* enable GPP CLK0 thru CLK1 */
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/* disable GPP CLK2 thru SLT_GFX_CLK */
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/* enable GPP CLK0 */
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/* disable GPP CLK1 thru SLT_GFX_CLK */
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u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
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*(misc_mem_clk_cntrl + 0) = 0xFF;
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*(misc_mem_clk_cntrl + 0) = 0x0F;
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*(misc_mem_clk_cntrl + 1) = 0x00;
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*(misc_mem_clk_cntrl + 2) = 0x00;
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*(misc_mem_clk_cntrl + 3) = 0x00;
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