mb/asus/p8h61-m_pro: Make devicetree prettier

Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.

Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/asus/p8h61-m_pro/devicetree.cb

@@ -30,6 +30,10 @@ chip northbridge/intel/sandybridge
 	end
 	register "pci_mmio_size" = "2048"
 	device domain 0x0 on
+		device pci 00.0 on end	# Host bridge
+		device pci 01.0 on end	# PCIe bridge for discrete graphics (PCIEX16_1)
+		device pci 02.0 on end	# Internal graphics VGA controller
+
 		chip southbridge/intel/bd82x6x	# Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"
 			register "gen1_dec" = "0x000c0291"	# HWM
@@ -37,6 +41,7 @@ chip northbridge/intel/sandybridge
 			register "sata_port_map" = "0x33"
 			register "spi_lvscc" = "0x2005"
 			register "spi_uvscc" = "0x2005"
+
 			device pci 16.0 on  end	# Management Engine Interface 1
 			device pci 16.1 off end	# Management Engine Interface 2
 			device pci 16.2 off end	# Management Engine IDE-R
@@ -113,7 +118,7 @@ chip northbridge/intel/sandybridge
 					end
 				end
 				chip drivers/pc80/tpm
-					device pnp 4e.0 on end		# TPM module
+					device pnp 4e.0 on end	# TPM
 				end
 			end
 			device pci 1f.2 on  end	# SATA Controller 1
@@ -121,8 +126,5 @@ chip northbridge/intel/sandybridge
 			device pci 1f.5 off end	# SATA Controller 2
 			device pci 1f.6 off end	# Thermal
 		end
-		device pci 00.0 on end # Host bridge
-		device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1)
-		device pci 02.0 on end # Internal graphics VGA controller
 	end
 end