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Add support for the Intel Atom D400/500- and N400-series integrated

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northbridge. Also add support for the very similar Q963/965 northbridge.
Tested: 
  D510: confirmed working, with MCHBAR enable code
  Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work

Untested:
  D410/D525/N400: should be the same northbridge

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood
2010-07-29 19:25:31 +00:00
parent 9b3cf8ef08
commit 23d98c768f
4 changed files with 42 additions and 0 deletions
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5
util/inteltool/inteltool.h
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@@ -62,6 +62,7 @@
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
#define PCI_DEVICE_ID_INTEL_Q965 0x2990
#define PCI_DEVICE_ID_INTEL_82975X 0x277c
#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
@@ -69,6 +70,10 @@
#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
#define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
/* untested, but almost identical to D-series */
#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */