Add support for the Intel Atom D400/500- and N400-series integrated
northbridge. Also add support for the very similar Q963/965 northbridge. Tested: D510: confirmed working, with MCHBAR enable code Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work Untested: D410/D525/N400: should be the same northbridge Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -47,6 +47,31 @@ int print_mchbar(struct pci_dev *nb)
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_Q965:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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mchbar_phys = pci_read_long(nb, 0x48);
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/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
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* If it isn't, try to set it. This may fail, because there is
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* some bit that locks that bit, and isn't in the public
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* datasheets.
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*/
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if(!(mchbar_phys & 1))
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{
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printf("Access to the MCHBAR is currently disabled, "\
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"attempting to enable.\n");
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mchbar_phys |= 0x1;
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pci_write_long(nb, 0x48, mchbar_phys);
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if(pci_read_long(nb, 0x48) & 1)
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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