Change the CBFS build process to use coreboot.rom

instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.

This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.

Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
  crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
  as it's done everywhere else
- change the default config of abuild to not
  provide ROM_IMAGE_SIZE values for the images
  in a CBFS configuration
- change abuild's crosscompile autodetection to
  not try to use "i386-elf-i386-elf-gcc" (which
  is bogus)

Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS

The changes in util/abuild/abuild are trivial and
abuild tested.

As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/config/failovercalculation.lb

@@ -10,8 +10,13 @@ else
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
 	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
     else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
-	default ROM_SECTION_OFFSET = 0
+	if CONFIG_CBFS
+		default ROM_SECTION_SIZE   = FALLBACK_SIZE
+		default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	else
+		default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+		default ROM_SECTION_OFFSET = 0
+	end
     end
 end
 

src/config/nofailovercalculation.lb

@@ -6,8 +6,13 @@ if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
 	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
 else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
+	if CONFIG_CBFS
+		default ROM_SECTION_SIZE   = FALLBACK_SIZE
+		default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE )
+	else
+		default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+		default ROM_SECTION_OFFSET = 0
+	end
 end
 
 ##

src/config/nofailovercalculation128.lb

@@ -6,8 +6,13 @@ if USE_FALLBACK_IMAGE
 	default ROM_SECTION_SIZE   = FALLBACK_SIZE
 	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
 else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
+	if CONFIG_CBFS
+		default ROM_SECTION_SIZE   = FALLBACK_SIZE
+		default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FALLBACK_SIZE )
+	else
+		default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+		default ROM_SECTION_OFFSET = 0
+	end
 end
 
 ##

src/mainboard/emulation/qemu-x86/Config.lb

@@ -3,14 +3,14 @@
 ## (coreboot plus bootloader) will live in the boot rom chip.
 ##
 default ROM_SIZE = 256 * 1024 
-default ROM_SECTION_SIZE   = ROM_SIZE
+default ROM_SECTION_SIZE   = ROM_IMAGE_SIZE
 default ROM_SECTION_OFFSET = 0
 
 ##
 ## Compute the start location and size size of
 ## The coreboot bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE            = ( ROM_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##

src/mainboard/emulation/qemu-x86/Options.lb

@@ -100,7 +100,7 @@ default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
 
 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
 default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+default FALLBACK_SIZE = ROM_IMAGE_SIZE
 
 ##
 ## Use a small 8K stack

src/mainboard/hp/dl145_g3/Options.lb

@@ -121,9 +121,7 @@ default ROM_SIZE=524288
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
 ##
-#default FALLBACK_SIZE=131072
-#256K
-default FALLBACK_SIZE=0x40000
+default FALLBACK_SIZE=ROM_IMAGE_SIZE
 
 #more 1M for pgtbl
 default CONFIG_LB_MEM_TOPK=2048
@@ -329,5 +327,9 @@ default  MAXIMUM_CONSOLE_LOGLEVEL=8
 ## Select power on after power fail setting
 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
 
+##
+## CBFS
+default CONFIG_CBFS=1
+
 ### End Options.lb
 end

src/mainboard/kontron/986lcd-m/Options.lb

@@ -249,7 +249,7 @@ default HEAP_SIZE=0x8000
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-default FALLBACK_SIZE=131072
+default FALLBACK_SIZE=ROM_IMAGE_SIZE
 
 ##
 ## coreboot C code runs at this location in RAM

src/mainboard/via/vt8454c/Options.lb

@@ -158,7 +158,7 @@ default CONFIG_IOAPIC=1
 
 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
 default ROM_IMAGE_SIZE = 65536
-default FALLBACK_SIZE = 131072
+default FALLBACK_SIZE = ROM_IMAGE_SIZE
 
 ##
 ## Use a small 8K stack