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cpu/intel/haswell: Allow tuning VR for C-state operations

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Apply commit ff0f460e76 (broadwell: Add configuration for tuning VR
for C-state operations) to Haswell, in preparation for unification.

Change-Id: Ib05974e8ed0f73c4f475b90065e8efb14555f9c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-10-28 23:48:56 +01:00
committed by Nico Huber
parent 9dcd1c1173
commit 242fd2810c
2 changed files with 50 additions and 2 deletions
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29
src/cpu/intel/haswell/chip.h
View File

@@ -3,6 +3,33 @@
/* Magic value used to locate this chip in the device tree */ /* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC #define SPEEDSTEP_APIC_MAGIC 0xACAC
#include <stdbool.h>
#include <stdint.h>
struct cpu_vr_config {
/*
* Minimum voltage for C6/C7 state:
* 0x67 = 1.6V (full swing)
* ...
* 0x79 = 1.7V
* ...
* 0x83 = 1.8V (no swing)
*/
uint8_t cpu_min_vid;
/*
* Set slow VR ramp rate on C-state exit:
* 0 = Fast VR ramp rate / 2
* 1 = Fast VR ramp rate / 4
* 2 = Fast VR ramp rate / 8
* 3 = Fast VR ramp rate / 16
*/
uint8_t slow_ramp_rate_set;
/* Enable slow VR ramp rate */
bool slow_ramp_rate_enable;
};
struct cpu_intel_haswell_config { struct cpu_intel_haswell_config {
int c1_battery; /* ACPI C1 on Battery Power */ int c1_battery; /* ACPI C1 on Battery Power */
int c2_battery; /* ACPI C2 on Battery Power */ int c2_battery; /* ACPI C2 on Battery Power */
@@ -13,4 +40,6 @@ struct cpu_intel_haswell_config {
int c3_acpower; /* ACPI C3 on AC Power */ int c3_acpower; /* ACPI C3 on AC Power */
int tcc_offset; /* TCC Activation Offset */ int tcc_offset; /* TCC Activation Offset */
struct cpu_vr_config vr_config;
}; };

23
src/cpu/intel/haswell/haswell_init.c
View File

@@ -249,8 +249,17 @@ static u32 pcode_mailbox_read(u32 command)
static void initialize_vr_config(void) static void initialize_vr_config(void)
{ {
struct cpu_vr_config vr_config = { 0 };
msr_t msr; msr_t msr;
const struct device *lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
if (lapic && lapic->chip_info) {
const struct cpu_intel_haswell_config *conf = lapic->chip_info;
vr_config = conf->vr_config;
}
printk(BIOS_DEBUG, "Initializing VR config.\n"); printk(BIOS_DEBUG, "Initializing VR config.\n");
/* Configure VR_CURRENT_CONFIG. */ /* Configure VR_CURRENT_CONFIG. */
@@ -280,13 +289,23 @@ static void initialize_vr_config(void)
msr.hi &= ~(1 << (51 - 32)); msr.hi &= ~(1 << (51 - 32));
/* Enable decay mode on C-state entry. */ /* Enable decay mode on C-state entry. */
msr.hi |= (1 << (52 - 32)); msr.hi |= (1 << (52 - 32));
/* Set the slow ramp rate */
if (haswell_is_ult()) { if (haswell_is_ult()) {
/* Set the slow ramp rate to be fast ramp rate / 4 */
msr.hi &= ~(0x3 << (53 - 32)); msr.hi &= ~(0x3 << (53 - 32));
msr.hi |= (0x01 << (53 - 32)); /* Configure the C-state exit ramp rate. */
if (vr_config.slow_ramp_rate_enable) {
/* Configured slow ramp rate. */
msr.hi |= ((vr_config.slow_ramp_rate_set & 0x3) << (53 - 32));
/* Set exit ramp rate to slow. */
msr.hi &= ~(1 << (50 - 32));
} else {
/* Fast ramp rate / 4. */
msr.hi |= (1 << (53 - 32));
}
} }
/* Set MIN_VID (31:24) to allow CPU to have full control. */ /* Set MIN_VID (31:24) to allow CPU to have full control. */
msr.lo &= ~0xff000000; msr.lo &= ~0xff000000;
msr.lo |= (vr_config.cpu_min_vid & 0xff) << 24;
wrmsr(MSR_VR_MISC_CONFIG, msr); wrmsr(MSR_VR_MISC_CONFIG, msr);
/* Configure VR_MISC_CONFIG2 MSR. */ /* Configure VR_MISC_CONFIG2 MSR. */