arch/x86: Drop CBMEM_TOP_BACKUP

Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.

Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/Kconfig

@@ -133,12 +133,6 @@ config NUM_IPI_STARTS
 	int
 	default 2
 
-config CBMEM_TOP_BACKUP
-	def_bool n
-	help
-	  Platform implements non-volatile storage to cache cbmem_top()
-	  over stage transitions and optionally also over S3 suspend.
-
 config PRERAM_CBMEM_CONSOLE_SIZE
 	hex
 	default 0xc00

src/arch/x86/Makefile.inc

@@ -164,7 +164,6 @@ romstage-y += post.c
 # gdt_init.S is included by entry32.inc when romstage is the first C
 # environment.
 romstage-y += gdt_init.S
-romstage-y += cbmem.c
 romstage-y += cpu_common.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
 romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S

src/arch/x86/cbmem.c

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <cbmem.h>
-
-#if CONFIG(CBMEM_TOP_BACKUP)
-
-void *cbmem_top_chipset(void)
-{
-	/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
-	return (void *)restore_top_of_low_cacheable();
-}
-
-#endif /* CBMEM_TOP_BACKUP */