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soc/mediatek/mt8188: devapc: Update permission for master domain setup

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Currently, all the masters controlled by DAPC are in domain 0. With
this setting, there is a potential security problem. For example, if a
certain master is somehow hacked, it may attempt to access registers
that it is not supposed to, with successful results. This is due to the
fact that, in the current setting, all masters are in domain 0 and can
access almost all registers. To prevent this problem, we assign masters
to different domains and restrict access to registers based on each
domain.

This patch updates the permission settings for domains 2, 3, 4, 5, 7,
8, 9, and 14, as these domains will be assigned masters in the upcoming
patch.

BUG=b:270657858
TEST=build pass

Change-Id: I6e95ddb5d84a09ff865d7615596430e25b69d3fc
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77861
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Nina Wu
2023-09-07 17:21:39 +08:00
committed by Yu-Ping Wu
parent 3748fca595
commit 244ec489f2
3 changed files with 284 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

392
src/soc/mediatek/mt8188/devapc.c
View File

@@ -6,32 +6,38 @@
static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
/* 0 */ /* 0 */
DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S", DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1", DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2", DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4", DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S", DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION2, FORBIDDEN3,
NO_PROTECTION2, FORBIDDEN4, NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1", DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("TINSYS_AO_S", DAPC_INFRA_AO_SYS0_ATTR("TINSYS_AO_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S", DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION2, FORBIDDEN3,
NO_PROTECTION2, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN4, NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S", DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
/* 10 */ /* 10 */
DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S", DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S",
@@ -39,18 +45,19 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S", DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S", DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
/* 20 */ /* 20 */
DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S", DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S", DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S",
@@ -62,7 +69,8 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S", DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S", DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S", DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S",
@@ -71,9 +79,9 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S", DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S", DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S",
@@ -96,11 +104,11 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S", DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S",
SEC_RW_ONLY, FORBIDDEN15), SEC_RW_ONLY, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S", DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("SRCLKEN_RC_APB_S", DAPC_INFRA_AO_SYS0_ATTR("SRCLKEN_RC_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S", DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1", DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1",
@@ -125,24 +133,30 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1", DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2", DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, SEC_RW_ONLY, FORBIDDEN4,
SEC_RW_ONLY, FORBIDDEN7),
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3", DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4", DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
/* 60 */ /* 60 */
DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5", DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, SEC_RW_ONLY, FORBIDDEN4,
SEC_RW_ONLY, FORBIDDEN7),
DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S", DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1", DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2", DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3", DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4", DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_INFRA_AO_SYS0_ATTR("L3C_S", DAPC_INFRA_AO_SYS0_ATTR("L3C_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1", DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1",
@@ -150,7 +164,7 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
DAPC_INFRA_AO_SYS0_ATTR("L3C_S-2", DAPC_INFRA_AO_SYS0_ATTR("L3C_S-2",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S", DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13),
/* 70 */ /* 70 */
DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S", DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
@@ -167,28 +181,28 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = { static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
/* 0 */ /* 0 */
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
/* 10 */ /* 10 */
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12",
@@ -202,7 +216,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19",
@@ -324,7 +338,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-74", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-74",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-75", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-75",
NO_PROTECTION, FORBIDDEN3), SEC_RW_ONLY, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-76", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-76",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-77", DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-77",
@@ -427,7 +441,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-1", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-1",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-2", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-2",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-3", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-3",
@@ -450,7 +464,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-11", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-11",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-12", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-12",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-13", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-13",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-14", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-14",
@@ -484,7 +498,7 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-27", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-27",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-28", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-28",
NO_PROTECTION, FORBIDDEN3), SEC_RW_ONLY, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-29", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-29",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-30", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-30",
@@ -524,9 +538,9 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
/* 170 */ /* 170 */
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-47", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-47",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-48", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-48",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-49", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-49",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-50", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-50",
@@ -580,9 +594,9 @@ static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-73", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-73",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-74", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-74",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-75", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-75",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION2, FORBIDDEN2),
DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-76", DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-76",
NO_PROTECTION, FORBIDDEN3), NO_PROTECTION, FORBIDDEN3),
/* 200 */ /* 200 */
@@ -913,97 +927,141 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = {
DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S", DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
/* 10 */ /* 10 */
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10", DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S", DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1", DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1", DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
/* 20 */ /* 20 */
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
/* 30 */ /* 30 */
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
/* 40 */ /* 40 */
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S", DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S", DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S", DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S",
@@ -1022,9 +1080,11 @@ static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = {
DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S", DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S", DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S", DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S", DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S",
SEC_RW_ONLY, FORBIDDEN15), SEC_RW_ONLY, FORBIDDEN15),
}; };
@@ -1046,7 +1106,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S", DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S", DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN),
DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S", DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S", DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S",
@@ -1103,7 +1163,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB1_S", DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB2_S", DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN),
DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB3_S", DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB3_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB4_S", DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB4_S",
@@ -1195,7 +1255,8 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S", DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S", DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION2, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S", DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S", DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S",
@@ -1206,7 +1267,7 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
/* 80 */ /* 80 */
DAPC_PERI2_AO_SYS0_ATTR("SRAMROM_APB_S", DAPC_PERI2_AO_SYS0_ATTR("SRAMROM_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_APB_S", DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("ECC_TOP_APB_S", DAPC_PERI2_AO_SYS0_ATTR("ECC_TOP_APB_S",
@@ -1222,18 +1283,19 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB1_S", DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB0_S", DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB0_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB1_S", DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
/* 90 */ /* 90 */
DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB2_S", DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB3_S", DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB3_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S", DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S", DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S", DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S",
SEC_RW_ONLY, FORBIDDEN15), SEC_RW_ONLY, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S", DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S",
@@ -1262,7 +1324,8 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S", DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S",
SEC_RW_ONLY, FORBIDDEN15), SEC_RW_ONLY, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_SUB_INFRA_APB_S",
@@ -1271,7 +1334,8 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S", DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S", DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S",
@@ -1279,11 +1343,13 @@ static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_PDN_APB_S", DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_PDN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB1_S", DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB1_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S", DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN7),
DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S", DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN6),
DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S", DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MDP_S", DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MDP_S",
@@ -1323,7 +1389,7 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = {
DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S", DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN13),
DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P2_S", DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P2_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P3_S", DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P3_S",
@@ -1331,7 +1397,8 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = {
DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN2, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN5, NO_PROTECTION, FORBIDDEN),
DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S",
@@ -1346,7 +1413,8 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = {
DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S",
@@ -1384,9 +1452,10 @@ static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = {
DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN8, NO_PROTECTION, FORBIDDEN4,
NO_PROTECTION, FORBIDDEN),
DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN13, NO_PROTECTION, FORBIDDEN),
DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S",
NO_PROTECTION, FORBIDDEN15), NO_PROTECTION, FORBIDDEN15),
DAPC_PERI_PAR_AO_SYS0_ATTR("PERICFG2_AO_APB_S", DAPC_PERI_PAR_AO_SYS0_ATTR("PERICFG2_AO_APB_S",
@@ -1547,10 +1616,48 @@ static void dump_peri_par_ao_apc(uintptr_t base)
read32(getreg(base, MAS_SEC_0))); read32(getreg(base, MAS_SEC_0)));
} }
static void dump_fmem_ao(uintptr_t base)
{
printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n",
base, read32(getreg(base, DOM_REMAP_0_0)));
}
static void dump_infra2_ao(uintptr_t base)
{
printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n",
base, read32(getreg(base, DOM_REMAP_0_0)));
}
static void infra_init(uintptr_t base) static void infra_init(uintptr_t base)
{ {
void *reg;
/* Side-band */ /* Side-band */
SET32_BITFIELDS(getreg(base, MAS_SEC_0), MCUPM_SEC, SECURE_TRANS); SET32_BITFIELDS(getreg(base, MAS_SEC_0), CPU_EB_SEC, SECURE_TRANS);
SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, SECURE_TRANS);
/*
* Domain Remap: INFRA (4-bit) -> MMSYS (2-bit)
* domain 0 -> domain 0
* domain 8 -> domain 1 (SCP)
* others -> domain 3
*/
reg = getreg(base, DOM_REMAP_2_0);
write32(reg, 0xFFFFFFFF);
SET32_BITFIELDS(reg,
TWO_BIT_DOM_REMAP_0, DOMAIN_0,
TWO_BIT_DOM_REMAP_8, DOMAIN_1);
/*
* Domain Remap: TINYSYS (3-bit) -> INFRA (4-bit)
* domain 0 -> domain 4 (DSP)
* others -> domain 15
*/
reg = getreg(base, DOM_REMAP_0_0);
write32(reg, 0xFFFFFFFF);
SET32_BITFIELDS(reg,
FOUR_BIT_DOM_REMAP_0, DOMAIN_4);
/* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */ /* TODO: Setup SCP, SSPM and MCUPM permissions in APC . */
set_infra_ao_apc(base); set_infra_ao_apc(base);
@@ -1558,8 +1665,23 @@ static void infra_init(uintptr_t base)
static void peri_init(uintptr_t base) static void peri_init(uintptr_t base)
{ {
void *reg;
/* Default APC setting */ /* Default APC setting */
set_peri_ao_apc(base); set_peri_ao_apc(base);
/*
* Domain Remap: INFRA (4-bit) -> TINYSYS (3-bit)
* domain 0 -> domain 0
* domain 4 -> domain 0 (DSP)
* others -> domain 7
*/
reg = getreg(base, DOM_REMAP_0_0);
write32(reg, 0xFFFFFFFF);
SET32_BITFIELDS(reg,
THREE_BIT_DOM_REMAP_0, DOMAIN_0,
THREE_BIT_DOM_REMAP_4, DOMAIN_0);
write32(getreg(base, DOM_REMAP_0_1), 0xFFFFFFFF);
} }
static void peri2_init(uintptr_t base) static void peri2_init(uintptr_t base)
@@ -1574,11 +1696,49 @@ static void peri_par_init(uintptr_t base)
set_peri_par_ao_apc(base); set_peri_par_ao_apc(base);
} }
static void fmem_master_init(uintptr_t base)
{
/*
* Domain Remap: TINYSYS to EMI (3-bit to 4-bit)
* 1. DSP from 0 to 4
* 2. others from XXX to 15
*/
SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0),
FOUR_BIT_DOM_REMAP_0, DOMAIN_4,
FOUR_BIT_DOM_REMAP_1, DOMAIN_15,
FOUR_BIT_DOM_REMAP_2, DOMAIN_15,
FOUR_BIT_DOM_REMAP_3, DOMAIN_15,
FOUR_BIT_DOM_REMAP_4, DOMAIN_15,
FOUR_BIT_DOM_REMAP_5, DOMAIN_15,
FOUR_BIT_DOM_REMAP_6, DOMAIN_15,
FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
}
static void infra2_master_init(uintptr_t base)
{
/*
* Domain Remap: TINYSYS to EMI (3-bit to 4-bit)
* 1. DSP from 0 to 4
* 2. others from XXX to 15
*/
SET32_BITFIELDS(getreg(base, DOM_REMAP_0_0),
FOUR_BIT_DOM_REMAP_0, DOMAIN_4,
FOUR_BIT_DOM_REMAP_1, DOMAIN_15,
FOUR_BIT_DOM_REMAP_2, DOMAIN_15,
FOUR_BIT_DOM_REMAP_3, DOMAIN_15,
FOUR_BIT_DOM_REMAP_4, DOMAIN_15,
FOUR_BIT_DOM_REMAP_5, DOMAIN_15,
FOUR_BIT_DOM_REMAP_6, DOMAIN_15,
FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
}
const struct devapc_init_ops devapc_init[] = { const struct devapc_init_ops devapc_init[] = {
{ DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc }, { DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc },
{ DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc },
{ DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc }, { DEVAPC_PERI2_AO_BASE, peri2_init, dump_peri2_ao_apc },
{ DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc }, { DEVAPC_PERI_PAR_AO_BASE, peri_par_init, dump_peri_par_ao_apc },
{ DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao },
{ DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao },
}; };
const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init); const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init);

2
src/soc/mediatek/mt8188/include/soc/addressmap.h
View File

@@ -41,6 +41,7 @@ enum {
DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0003C000,
PERI_PAR_AO_BASE = IO_PHYS + 0x00040000, PERI_PAR_AO_BASE = IO_PHYS + 0x00040000,
FMEM_AO_BASE = IO_PHYS + 0x00042000, FMEM_AO_BASE = IO_PHYS + 0x00042000,
DEVAPC_FMEM_AO_BASE = IO_PHYS + 0x00044000,
DBG_TRACKER_BASE = IO_PHYS + 0x00208000, DBG_TRACKER_BASE = IO_PHYS + 0x00208000,
PERI_TRACKER_BASE = IO_PHYS + 0x00218000, PERI_TRACKER_BASE = IO_PHYS + 0x00218000,
EMI0_BASE = IO_PHYS + 0x00219000, EMI0_BASE = IO_PHYS + 0x00219000,
@@ -52,6 +53,7 @@ enum {
I2C4_DMA_BASE = IO_PHYS + 0x00220380, I2C4_DMA_BASE = IO_PHYS + 0x00220380,
I2C5_DMA_BASE = IO_PHYS + 0x00220480, I2C5_DMA_BASE = IO_PHYS + 0x00220480,
I2C6_DMA_BASE = IO_PHYS + 0x00220600, I2C6_DMA_BASE = IO_PHYS + 0x00220600,
DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000,
DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000,
INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000,
SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000,

9
src/soc/mediatek/mt8188/include/soc/devapc.h
View File

@@ -11,13 +11,14 @@ enum devapc_ao_offset {
SYS0_D0_APC_0 = 0x00000, SYS0_D0_APC_0 = 0x00000,
SYS1_D0_APC_0 = 0x01000, SYS1_D0_APC_0 = 0x01000,
SYS2_D0_APC_0 = 0x02000, SYS2_D0_APC_0 = 0x02000,
DOM_REMAP_0_0 = 0x00800,
DOM_REMAP_0_1 = 0x00804,
DOM_REMAP_2_0 = 0x00820,
MAS_DOM_0 = 0x00900, MAS_DOM_0 = 0x00900,
MAS_SEC_0 = 0x00A00, MAS_SEC_0 = 0x00A00,
AO_APC_CON = 0x00F00, AO_APC_CON = 0x00F00,
}; };
DEFINE_BIT(MCUPM_SEC, 1)
/****************************************************************************** /******************************************************************************
* STRUCTURE DEFINITION * STRUCTURE DEFINITION
******************************************************************************/ ******************************************************************************/
@@ -54,6 +55,8 @@ enum devapc_cfg_index {
/****************************************************************************** /******************************************************************************
* Bit Field DEFINITION * Bit Field DEFINITION
******************************************************************************/ ******************************************************************************/
/* TODO */ /* INFRA */
DEFINE_BIT(CPU_EB_SEC, 1)
DEFINE_BIT(SCP_SSPM_SEC, 2)
#endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */ #endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */