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soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T

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It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.

FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.

Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.

Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN

Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2019-11-25 11:57:28 +05:30
parent 0d2dbcab5f
commit 24ab1c5db6
7 changed files with 50 additions and 40 deletions
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15
src/drivers/intel/fsp2_0/Kconfig
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@@ -37,21 +37,6 @@ config ADD_FSP_BINARIES
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
use the FSP-T binary and it is not added.
config CPU_MICROCODE_CBFS_LEN
hex "Microcode update region length in bytes"
depends on FSP_CAR
default 0x0
help
The length in bytes of the microcode update region.
config CPU_MICROCODE_CBFS_LOC
hex "Microcode update base address in CBFS"
depends on FSP_CAR
default 0x0
help
The location (base address) in CBFS that contains the
microcode update binary.
config FSP_T_CBFS
string "Name of FSP-T in CBFS"
depends on FSP_CAR