soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T

It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.

FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.

Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.

Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN

Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37187
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/skylake/fspcar.c

@@ -23,10 +23,19 @@ const FSPT_UPD temp_ram_init_params = {
 		.Reserved = {0},
 	},
 	.FsptCoreUpd = {
-		.MicrocodeRegionBase =
-			(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LOC,
-		.MicrocodeRegionSize =
-			(uint32_t)CONFIG_CPU_MICROCODE_CBFS_LEN,
+		/*
+		 * It is a requirement for firmware to have Firmware Interface Table
+		 * (FIT), which contains pointers to each microcode update.
+		 * The microcode update is loaded for all logical processors before
+		 * cpu reset vector.
+		 *
+		 * All SoC since Gen-4 has above mechanism in place to load microcode
+		 * even before hitting CPU reset vector. Hence skipping FSP-T loading
+		 * microcode after CPU reset by passing '0' value to
+		 * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength.
+		 */
+		.MicrocodeRegionBase = 0,
+		.MicrocodeRegionLength = 0,
 		.CodeRegionBase =
 			(uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE),
 		.CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,