From 24b1c54226d5a676547c5b0203dd5787fa5a1143 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 2 Jun 2021 13:08:15 -0600 Subject: [PATCH] soc/intel/alderlake: Set SaIpuEnable UPD according to devicetree The SaIpuEnable UPD is not currently being touched by coreboot; set it according to the enabled status of the corresponding devicetree node. TEST=turn ipu device on or off in devicetree, see device enumerated or not in OS, according to the devicetree setting. Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/55143 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/romstage/fsp_params.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fdfb65b6d9..abfc1d91ee 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -207,6 +207,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, dev = pcidev_path_on_root(SA_DEVFN_TBT3); m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); + /* IPU */ + dev = pcidev_path_on_root(SA_DEVFN_IPU); + m_cfg->SaIpuEnable = is_dev_enabled(dev); + /* VT-d config */ m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS;