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soc/skl/vr_config: Add VR config for SKL-S/H/U/Y

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Icc/Loadline automatic detection is supported only for FSP2.0

These changes are in accordance with the documentation:
[*] S-Platforms, Document Number: 332687-008EN
[*] H-Platforms, Document Number: 332986-010EN
[*] U/Y-Platforms, Document Number: 332990-008EN

Change-Id: I8e517d8230c251e0cd4b1d4f1b9292c3df80cb19
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Maxim Polyakov
2019-08-29 18:40:19 +03:00
committed by Patrick Georgi
parent bec78e32d6
commit 24ba85002a
2 changed files with 151 additions and 106 deletions
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28
src/soc/intel/skylake/include/soc/vr_config.h
View File

@@ -83,6 +83,16 @@ enum vr_domain {
VR_GT_SLICED, VR_GT_SLICED,
NUM_VR_DOMAINS NUM_VR_DOMAINS
}; };
#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \
{ \
[VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \
[VR_IA_CORE] = VR_CFG_AMP(ia), \
[VR_RING] = VR_CFG_AMP(0), \
[VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \
[VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \
}
#else #else
/* VrConfig Settings for 4 domains /* VrConfig Settings for 4 domains
* 0 = System Agent, 1 = IA Core, * 0 = System Agent, 1 = IA Core,
@@ -95,8 +105,26 @@ enum vr_domain {
VR_GT_SLICED, VR_GT_SLICED,
NUM_VR_DOMAINS NUM_VR_DOMAINS
}; };
#define VR_CFG_ALL_DOMAINS_ICC(sa, ia, gt_unsl, gt_sl) \
{ \
[VR_SYSTEM_AGENT] = VR_CFG_AMP(sa), \
[VR_IA_CORE] = VR_CFG_AMP(ia), \
[VR_GT_UNSLICED] = VR_CFG_AMP(gt_unsl), \
[VR_GT_SLICED] = VR_CFG_AMP(gt_sl), \
}
#endif #endif
#define VR_CFG_ALL_DOMAINS_LOADLINE(sa, ia, gt_unsl, gt_sl) \
{ \
[VR_SYSTEM_AGENT] = VR_CFG_MOHMS(sa), \
[VR_IA_CORE] = VR_CFG_MOHMS(ia), \
[VR_GT_UNSLICED] = VR_CFG_MOHMS(gt_unsl), \
[VR_GT_SLICED] = VR_CFG_MOHMS(gt_sl), \
}
void fill_vr_domain_config(void *params, void fill_vr_domain_config(void *params,
int domain, const struct vr_config *cfg); int domain, const struct vr_config *cfg);
#endif #endif

229
src/soc/intel/skylake/vr_config.c
View File

@@ -92,113 +92,139 @@ static uint16_t get_sku_icc_max(int domain)
{ {
const uint16_t tdp = cpu_get_power_max(); const uint16_t tdp = cpu_get_power_max();
static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; static uint16_t mch_id = 0, igd_id = 0;
if (!mch_id) { if (!mch_id) {
struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
mch_id = pci_read_config16(dev, PCI_DEVICE_ID); mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
} }
if (!igd_id) { if (!igd_id) {
struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (dev) igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
igd_id = pci_read_config16(dev, PCI_DEVICE_ID);
else
igd_id = 0xffff;
}
if (!lpc_id) {
struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
lpc_id = pci_read_config16(dev, PCI_DEVICE_ID);
} }
/* /*
* Iccmax table from Doc #559100 Section 7.2 DC Specifications, the * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the
* Iccmax is the same among KBL-Y but KBL-U/R. * Iccmax is the same among KBL-Y but KBL-U/R.
* Addendum for AML-Y #594883, IccMax for IA core is 28A. * Addendum for AML-Y #594883, IccMax for IA core is 28A.
* KBL-S #335195, KBL-H #335190 * KBL-S #335195, KBL-H #335190, SKL-S #332687, SKL-H #332986,
* +----------------+-------------+---------------+------+-----+ * SKL-U/Y #332990
* | Domain/Setting | SA | IA | GTUS | GTS | *
* +----------------+-------------+---------------+------+-----+ * Platform Segment SA IA GT (GT/GTx)
* | IccMax(KBL-S) | 11.1A | 100A | 48A | 48A | * ---------------------------------------------------------------------
* | | | ... | 45A | 45A | * KBL/SKL-S (95W) quad 11.1 100 45
* | | | 40A | 35A | 35A | * SKL-S (80W) quad 11.1 82 45
* +----------------+-------------+---------------+------+-----+ * KBL/SKL-S (65W) quad 11.1 79 45
* | IccMax(KBL-H) | 11.1A (45W) | 68A | 55A | 55A | * SKL-S (45W) quad 11.1 70 0
* | | 6.6A (18W) | 60A | | | * KBL/SKL-S (35W) quad 11.1 66 35
* +----------------+-------------+---------------+------+-----+ * SKL-S (25W) quad 11.1 55 35
* | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | *
* | | 4.5A(Others)| 29A(P/C) | | | * KBL/SKL-S (54W) dual 11.1 58 48
* | | | 32A(i3/i5) | | | * KBL/SKL-S (51W) dual 11.1 45 48
* +----------------+-------------+---------------+------+-----+ * KBL/SKL-S (35W) dual 11.1 40 48
* | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | *
* +----------------+-------------+---------------+------+-----+ * SKL-H + OPC (65W) GT4 quad 8 74 105/24
* | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | * SKL-H + OPC (45W) GT4 quad 8 74 94/20
* +----------------+-------------+---------------+------+-----+ * SKL-H + OPC (35W) GT4 quad 8 66 94/20
*
* SKL-H (35W) GT2 dual 11.1 60 55
*
* KBL/SKL-H (45W) GT2 quad 11.1 68 55
* KBL-H (18W) GT2 quad 6.6 60 55
*
* SKL-U + OPC (28W) GT3 dual 5.1 32 57/19
* SKL-U + OPC (15W) GT3 dual 5.1 29 57/19
* SKL-U (15W) GT2 dual 4.5 29 31
*
* KBL-U/R + OPC (28W) GT3 dual 5.1 32 57/19
* KBL-U/R + OPC (15W) GT3 dual 5.1 32 57/19
*
* KBL-U/R (15W) GT2 quad 6 64 31
* KBL-U/R (15W) GT1/2 dual 4.5 32 31
* KBL-U/R (15W) GT2 quad 4.5 29 31
*
* SKL/KBL-Y (6W) 4.1 24 24
* SKL/KBL-Y (4.5W) 4.1 24 24
*/ */
switch (mch_id) { switch (mch_id) {
case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_S: { case PCI_DEVICE_ID_INTEL_KBL_ID_S: {
uint16_t icc_max[NUM_VR_DOMAINS] = { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 48, 48);
VR_CFG_AMP(11.1),
VR_CFG_AMP(40),
VR_CFG_AMP(48),
VR_CFG_AMP(48),
};
if (tdp >= 54) if (tdp >= 54)
icc_max[VR_IA_CORE] = VR_CFG_AMP(58); icc_max[VR_IA_CORE] = VR_CFG_AMP(58);
else if (tdp >= 51) else if (tdp >= 51)
icc_max[VR_IA_CORE] = VR_CFG_AMP(45); icc_max[VR_IA_CORE] = VR_CFG_AMP(45);
return icc_max[domain]; return icc_max[domain];
} }
case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { case PCI_DEVICE_ID_INTEL_KBL_ID_DT: {
uint16_t icc_max[NUM_VR_DOMAINS] = { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 45, 45);
VR_CFG_AMP(11.1),
VR_CFG_AMP(66),
VR_CFG_AMP(45),
VR_CFG_AMP(45),
};
if (tdp >= 91) if (tdp >= 91)
icc_max[VR_IA_CORE] = VR_CFG_AMP(100); icc_max[VR_IA_CORE] = VR_CFG_AMP(100);
else if (tdp >= 80)
icc_max[VR_IA_CORE] = VR_CFG_AMP(82);
else if (tdp >= 65) else if (tdp >= 65)
icc_max[VR_IA_CORE] = VR_CFG_AMP(79); icc_max[VR_IA_CORE] = VR_CFG_AMP(79);
else if (tdp >= 35) { else if (tdp >= 45) {
icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35); icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
icc_max[VR_GT_SLICED] = 0;
icc_max[VR_GT_UNSLICED] = 0;
} else if (tdp >= 25) {
if (tdp >= 35)
icc_max[VR_IA_CORE] = VR_CFG_AMP(66);
icc_max[VR_GT_SLICED] = VR_CFG_AMP(35); icc_max[VR_GT_SLICED] = VR_CFG_AMP(35);
icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35);
} }
return icc_max[domain]; return icc_max[domain];
} }
case PCI_DEVICE_ID_INTEL_KBL_ID_H: { case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: {
uint16_t icc_max[NUM_VR_DOMAINS] = { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 94, 20);
VR_CFG_AMP(6.6),
VR_CFG_AMP(60),
VR_CFG_AMP(55),
VR_CFG_AMP(55),
};
if (tdp >= 45) { if (tdp >= 45) {
icc_max[VR_IA_CORE] = VR_CFG_AMP(74);
if (tdp >= 65) {
icc_max[VR_GT_SLICED] = VR_CFG_AMP(105);
icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(24);
}
}
return icc_max[domain];
}
case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */
case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_H: {
uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6.6, 60, 55, 55);
if (tdp >= 35) {
if (tdp >= 45)
icc_max[VR_IA_CORE] = VR_CFG_AMP(68);
icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1);
icc_max[VR_IA_CORE] = VR_CFG_AMP(68);
} }
return icc_max[domain]; return icc_max[domain];
} }
case PCI_DEVICE_ID_INTEL_SKL_ID_U: {
uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(5.1, 29, 57, 19);
if (tdp >= 28)
icc_max[VR_IA_CORE] = VR_CFG_AMP(32);
else if (igd_id != PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) {
const uint16_t icc_max_gt2[NUM_VR_DOMAINS] =
VR_CFG_ALL_DOMAINS_ICC(4.5, 29, 31, 31);
return icc_max_gt2[domain];
}
return icc_max[domain];
}
case PCI_DEVICE_ID_INTEL_KBL_U_R: { case PCI_DEVICE_ID_INTEL_KBL_U_R: {
static const uint16_t icc_max[NUM_VR_DOMAINS] = { const uint16_t icc_max[NUM_VR_DOMAINS] =
VR_CFG_AMP(6), VR_CFG_ALL_DOMAINS_ICC(6, 64, 31, 31);
VR_CFG_AMP(64),
VR_CFG_AMP(31),
VR_CFG_AMP(31),
};
return icc_max[domain]; return icc_max[domain];
} }
case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { case PCI_DEVICE_ID_INTEL_KBL_ID_Y: {
uint16_t icc_max[NUM_VR_DOMAINS] = { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.1, 24, 24, 24);
VR_CFG_AMP(4.1),
VR_CFG_AMP(24),
VR_CFG_AMP(24),
VR_CFG_AMP(24),
};
if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX)
icc_max[VR_IA_CORE] = VR_CFG_AMP(28); icc_max[VR_IA_CORE] = VR_CFG_AMP(28);
@@ -206,12 +232,7 @@ static uint16_t get_sku_icc_max(int domain)
return icc_max[domain]; return icc_max[domain];
} }
case PCI_DEVICE_ID_INTEL_KBL_ID_U: { case PCI_DEVICE_ID_INTEL_KBL_ID_U: {
uint16_t icc_max[NUM_VR_DOMAINS] = { uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31);
VR_CFG_AMP(4.5),
VR_CFG_AMP(32),
VR_CFG_AMP(31),
VR_CFG_AMP(31),
};
if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) ||
(igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2))
@@ -220,7 +241,7 @@ static uint16_t get_sku_icc_max(int domain)
return icc_max[domain]; return icc_max[domain];
} }
default: default:
printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id);
} }
return 0; return 0;
} }
@@ -231,62 +252,58 @@ static uint16_t get_sku_ac_dc_loadline(const int domain)
static uint16_t mch_id = 0, igd_id = 0; static uint16_t mch_id = 0, igd_id = 0;
if (!mch_id) { if (!mch_id) {
struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
mch_id = pci_read_config16(dev, PCI_DEVICE_ID); mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
} }
if (!igd_id) { if (!igd_id) {
struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (dev) igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
igd_id = pci_read_config16(dev, PCI_DEVICE_ID);
else
igd_id = 0xffff;
} }
switch (mch_id) { switch (mch_id) {
case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: {
static const uint16_t loadline[NUM_VR_DOMAINS] = { /* SA Loadline is not specified */
VR_CFG_MOHMS(0), /* Not specified */ const uint16_t loadline[NUM_VR_DOMAINS] =
VR_CFG_MOHMS(2.1), VR_CFG_ALL_DOMAINS_LOADLINE(0, 2.1, 3.1, 3.1);
VR_CFG_MOHMS(3.1),
VR_CFG_MOHMS(3.1),
};
return loadline[domain]; return loadline[domain];
} }
case PCI_DEVICE_ID_INTEL_SKL_ID_H_2: /* fallthrough */
case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */
case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_H: { case PCI_DEVICE_ID_INTEL_KBL_ID_H: {
static const uint16_t loadline[NUM_VR_DOMAINS] = { const uint16_t loadline[NUM_VR_DOMAINS] =
VR_CFG_MOHMS(10), VR_CFG_ALL_DOMAINS_LOADLINE(10, 1.8, 2.65, 2.65);
VR_CFG_MOHMS(1.8),
VR_CFG_MOHMS(2.65), if (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM) {
VR_CFG_MOHMS(2.65), const uint16_t loadline_gt4[NUM_VR_DOMAINS] =
}; VR_CFG_ALL_DOMAINS_LOADLINE(6, 1.6, 1.4, 6);
return loadline_gt4[domain];
}
return loadline[domain]; return loadline[domain];
} }
case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { case PCI_DEVICE_ID_INTEL_KBL_ID_Y: {
uint16_t loadline[NUM_VR_DOMAINS] = { uint16_t loadline[NUM_VR_DOMAINS] =
VR_CFG_MOHMS(18), VR_CFG_ALL_DOMAINS_LOADLINE(18, 5.9, 5.7, 5.7);
VR_CFG_MOHMS(5.9),
VR_CFG_MOHMS(5.7),
VR_CFG_MOHMS(5.7),
};
if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX)
loadline[VR_IA_CORE] = VR_CFG_MOHMS(4); loadline[VR_IA_CORE] = VR_CFG_MOHMS(4);
return loadline[domain]; return loadline[domain];
} }
case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ case PCI_DEVICE_ID_INTEL_SKL_ID_U: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */
case PCI_DEVICE_ID_INTEL_KBL_ID_U: { case PCI_DEVICE_ID_INTEL_KBL_ID_U: {
uint16_t loadline[NUM_VR_DOMAINS] = { uint16_t loadline[NUM_VR_DOMAINS] =
VR_CFG_MOHMS(10.3), VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1);
VR_CFG_MOHMS(2.4),
VR_CFG_MOHMS(3.1),
VR_CFG_MOHMS(3.1),
};
if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) || if ((igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) ||
(igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2) ||
(igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) ||
(igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) { (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) {
loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2); loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6);
@@ -295,7 +312,7 @@ static uint16_t get_sku_ac_dc_loadline(const int domain)
return loadline[domain]; return loadline[domain];
} }
default: default:
printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id);
} }
return 0; return 0;
} }