x86: Unify arch/io.h and arch/romcc_io.h

Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/northbridge/amd/amdfam10/bootblock.c

@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "northbridge/amd/amdfam10/early_ht.c"
 

src/northbridge/amd/amdk8/bootblock.c

@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "northbridge/amd/amdk8/early_ht.c"
 

src/northbridge/amd/amdk8/coherent_ht.c

@@ -67,7 +67,7 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include <stdlib.h>
-#include "arch/romcc_io.h"
+#include <arch/io.h>
 #include <pc80/mc146818rtc.h>
 #if CONFIG_HAVE_OPTION_TABLE
 #include "option_table.h"

src/northbridge/intel/e7505/debug.c

@@ -3,7 +3,6 @@
 #include <console/console.h>
 #include <stdlib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 
 #include "raminit.h"

src/northbridge/intel/e7505/raminit.c

@@ -15,7 +15,6 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <arch/cpu.h>
 #include <stdlib.h>
 #include <console/console.h>

src/northbridge/intel/gm45/early_init.c

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "gm45.h"
 
 void gm45_early_init(void)

src/northbridge/intel/gm45/early_reset.c

@@ -21,7 +21,6 @@
 
 #include <types.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "gm45.h"
 
 void gm45_early_reset(void/*const timings_t *const timings*/)

src/northbridge/intel/gm45/igd.c

@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 

src/northbridge/intel/gm45/iommu.c

@@ -23,7 +23,6 @@
 #include <string.h>
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <arch/acpi.h>
 

src/northbridge/intel/gm45/pcie.c

@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>

src/northbridge/intel/gm45/pm.c

@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <console/console.h>

src/northbridge/intel/gm45/ram_calc.c

@@ -19,9 +19,11 @@
  * MA 02110-1301 USA
  */
 
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "gm45.h"

src/northbridge/intel/gm45/raminit.c

@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <spd.h>

src/northbridge/intel/gm45/thermal.c

@@ -23,7 +23,6 @@
 #include <stddef.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <spd.h>

src/northbridge/intel/haswell/bootblock.c

@@ -1,5 +1,4 @@
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 /* Just re-define this instead of including haswell.h. It blows up romcc. */
 #define PCIEXBAR	0x60

src/northbridge/intel/haswell/early_init.c

@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include "haswell.h"

src/northbridge/intel/haswell/finalize.c

@@ -19,7 +19,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <stdlib.h>
 #include "haswell.h"
 

src/northbridge/intel/haswell/raminit.c

@@ -21,7 +21,6 @@
 #include <string.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>

src/northbridge/intel/haswell/report_platform.c

@@ -22,9 +22,7 @@
 #include <string.h>
 #include "southbridge/intel/lynxpoint/pch.h"
 #include <arch/io.h>
-#include <arch/io.h>
 #include <cpu/x86/msr.h>
-#include <arch/romcc_io.h>
 #include "haswell.h"
 
 static void report_cpu_info(void)

src/northbridge/intel/i440bx/debug.c

@@ -1,6 +1,5 @@
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 #include "raminit.h"
 #include <spd.h>

src/northbridge/intel/i440bx/raminit.c

@@ -24,7 +24,6 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i440bx.h"

src/northbridge/intel/i5000/raminit.c

@@ -21,7 +21,6 @@
 
 #include "raminit.h"
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>

src/northbridge/intel/i5000/raminit.h

@@ -24,7 +24,6 @@
 
 #include <types.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 
 #define I5000_MAX_BRANCH 2
 #define I5000_MAX_CHANNEL 2

src/northbridge/intel/i82810/debug.c

@@ -1,6 +1,5 @@
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <spd.h>
 #include "i82810.h"
 #include "raminit.h"

src/northbridge/intel/i82810/raminit.c

@@ -24,7 +24,6 @@
 #include <delay.h>
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i82810.h"

src/northbridge/intel/i82830/smihandler.c

@@ -22,7 +22,6 @@
 #include <types.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>

src/northbridge/intel/i945/debug.c

@@ -22,7 +22,6 @@
 #include <spd.h>
 #include <lib.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <console/console.h>
 #include "i945.h"

src/northbridge/intel/i945/early_init.c

@@ -21,7 +21,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include "i945.h"
 #include "pcie_config.c"

src/northbridge/intel/i945/raminit.c

@@ -23,7 +23,7 @@
 #include <pc80/mc146818rtc.h>
 #include <spd.h>
 #include <string.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 #include "raminit.h"
 #include "i945.h"
 #include <cbmem.h>

src/northbridge/intel/sandybridge/early_init.c

@@ -22,7 +22,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include "sandybridge.h"

src/northbridge/intel/sandybridge/finalize.c

@@ -19,7 +19,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <stdlib.h>
 #include "pcie_config.c"
 #include "sandybridge.h"

src/northbridge/intel/sandybridge/raminit.c

@@ -21,7 +21,6 @@
 #include <string.h>
 #include <arch/hlt.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>

src/northbridge/intel/sandybridge/report_platform.c

@@ -22,7 +22,6 @@
 #include <string.h>
 #include "southbridge/intel/bd82x6x/pch.h"
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include "sandybridge.h"
 
 static void report_cpu_info(void)

src/northbridge/intel/sch/port_access.c

@@ -17,9 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#ifndef __PRE_RAM__
+#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#endif
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>

src/northbridge/via/cx700/early_serial.c

@@ -21,7 +21,7 @@
  * Enable the serial devices on the VIA CX700
  */
 
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 static void cx700_writepnpaddr(u8 val)
 {

src/northbridge/via/vx800/early_serial.c

@@ -20,7 +20,7 @@
 /*
  * Enable the serial devices on the VIA
  */
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 /* The base address is 0x15c, 0x2e, depending on config bytes */
 

src/northbridge/via/vx800/examples/romstage.c

@@ -24,7 +24,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "console/console.c"
 #include "lib/ramtest.c"

src/northbridge/via/vx800/pci_rawops.h

@@ -22,7 +22,7 @@
 #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
 
 #include <stdint.h>
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 struct VIA_PCI_REG_INIT_TABLE {
 	u8 ChipRevisionStart;