nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.c
There's nothing Sandy Bridge specific in this code. Make it available on all platforms to reduce code duplication. Tested on Lenovo T430: SMBIOS entry 17 is still valid. Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/28213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Felix Held
parent
4d2af9df7c
commit
24efe73dfd
@ -16,7 +16,6 @@
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*/
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#include <console/console.h>
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#include <console/usb.h>
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#include <commonlib/region.h>
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#include <bootmode.h>
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#include <string.h>
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@ -29,8 +28,6 @@
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#include <southbridge/intel/common/smbus.h>
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <smbios.h>
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#include <memory_info.h>
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#include <lib.h>
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#include "raminit_native.h"
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#include "raminit_common.h"
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@ -81,67 +78,14 @@ static void disable_channel(ramctr_timing *ctrl, int channel) {
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*/
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static void fill_smbios17(ramctr_timing *ctrl)
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{
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struct memory_info *mem_info;
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int channel, slot;
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struct dimm_info *dimm;
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uint16_t ddr_freq;
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dimm_info *info = &ctrl->info;
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ddr_freq = (1000 << 8) / ctrl->tCK;
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/*
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* Allocate CBMEM area for DIMM information used to populate SMBIOS
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* table 17
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*/
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mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
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printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
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if (!mem_info)
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return;
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memset(mem_info, 0, sizeof(*mem_info));
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const u16 ddr_freq = (1000 << 8) / ctrl->tCK;
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FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) {
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dimm = &mem_info->dimm[mem_info->dimm_cnt];
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if (info->dimm[channel][slot].size_mb) {
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dimm->ddr_type = MEMORY_TYPE_DDR3;
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dimm->ddr_frequency = ddr_freq;
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dimm->dimm_size = info->dimm[channel][slot].size_mb;
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dimm->channel_num = channel;
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dimm->rank_per_dimm = info->dimm[channel][slot].ranks;
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dimm->dimm_num = slot;
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memcpy(dimm->module_part_number,
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info->dimm[channel][slot].part_number, 16);
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dimm->mod_id = info->dimm[channel][slot].manufacturer_id;
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switch (info->dimm[channel][slot].dimm_type) {
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case SPD_DIMM_TYPE_SO_DIMM:
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dimm->mod_type = SPD_SODIMM;
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break;
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case SPD_DIMM_TYPE_72B_SO_CDIMM:
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dimm->mod_type = SPD_72B_SO_CDIMM;
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break;
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case SPD_DIMM_TYPE_72B_SO_RDIMM:
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dimm->mod_type = SPD_72B_SO_RDIMM;
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break;
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case SPD_DIMM_TYPE_UDIMM:
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dimm->mod_type = SPD_UDIMM;
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break;
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case SPD_DIMM_TYPE_RDIMM:
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dimm->mod_type = SPD_RDIMM;
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break;
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case SPD_DIMM_TYPE_UNDEFINED:
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default:
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dimm->mod_type = SPD_UNDEFINED;
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break;
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}
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dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
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memcpy(dimm->serial, info->dimm[channel][slot].serial,
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MIN(sizeof(dimm->serial),
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sizeof(info->dimm[channel][slot].serial)));
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mem_info->dimm_cnt++;
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}
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enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq,
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&ctrl->info.dimm[channel][slot]);
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if (ret != CB_SUCCESS)
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printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n");
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}
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}
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