northbridge/intel/i3100: Unify UDELAY selection

Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i3100 boards in the chipset.

Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13786
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/intel/eagleheights/Kconfig

@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select UDELAY_TSC
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_1024
 

src/mainboard/intel/mtarvon/Kconfig

@@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_INTEL_I3100
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_2048
 
 config MAINBOARD_DIR

src/mainboard/intel/truxton/Kconfig

@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
-	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_2048
 
 config MAINBOARD_DIR

src/mainboard/intel/truxton/romstage.c

@@ -21,7 +21,6 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
-#include "drivers/pc80/udelay_io.c"
 #include <console/console.h>
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"

src/northbridge/intel/i3100/Kconfig

@@ -1,6 +1,7 @@
 config NORTHBRIDGE_INTEL_I3100
 	bool
 	select LATE_CBMEM_INIT
+	select UDELAY_IO
 
 if NORTHBRIDGE_INTEL_I3100
 config DIMM_MAP_LOGICAL

src/northbridge/intel/i3100/raminit_ep80579.c

@@ -19,6 +19,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/intel/speedstep.h>
 #include <lib.h>
+#include <delay.h>
 #include "raminit_ep80579.h"
 #include "ep80579.h"