soc/amd/stoneyridge: Move GPIO support to common

The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product.  Move the basic support into a common
directory.

Each product's pin availability, MUXes, and other details must remain
specific to the product.

The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available.  The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices.  This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.

BUG=b:131682806

Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
2019-05-02 17:27:57 -06:00
committed by Martin Roth
parent eb5b0d05a7
commit 251d305e73
17 changed files with 663 additions and 575 deletions

View File

@@ -317,9 +317,9 @@ static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
{
if (gpio_num >= GPIO_TOTAL_PINS) {
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, GPIO_TOTAL_PINS);
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);
@@ -347,9 +347,9 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
{
if (gpio_num >= GPIO_TOTAL_PINS) {
if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
" %d\n", gpio_num, GPIO_TOTAL_PINS);
" %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
return -1;
}
uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num);