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mb/*: devicetree: drop now unneeded USBx_PORT_EMPTY

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Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).

Thus, drop the setting from all devicetrees.

Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Michael Niewöhner
2020-09-05 13:47:11 +02:00
committed by Michael Niewöhner
parent 056d552357
commit 2539a67273
43 changed files with 0 additions and 211 deletions
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3
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@@ -14,9 +14,6 @@ chip soc/intel/cannonlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_EMPTY"
register "usb2_ports[7]" = "USB2_PORT_EMPTY"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"

2
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
View File

@@ -15,12 +15,10 @@ chip soc/intel/cannonlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
register "usb2_ports[6]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[7]" = "USB2_PORT_MID(OC1)"
register "usb2_ports[8]" = "USB2_PORT_EMPTY"
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[10]" = "USB2_PORT_MID(OC3)"
register "usb2_ports[11]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[12]" = "USB2_PORT_MID(OC6)"
register "usb2_ports[13]" = "USB2_PORT_EMPTY"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC4)"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"

2
src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
View File

@@ -93,8 +93,6 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled
register "SsicPortEnable" = "1" # Enable SSIC for WWAN

2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@@ -29,8 +29,6 @@ chip soc/intel/tigerlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # USB3/USB2 Flex Connector
# CPU replacement check
register "CpuReplacementCheck" = "1"

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -22,14 +22,10 @@ chip soc/intel/tigerlake
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3
register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Not used
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # USB3/USB2 Flex Connector
# CPU replacement check