soc/intel/lunarlake: Support stepping A0_2

Details:
- Add support for new Lunar Lake MCH ID 0x6410
- Add new CPU id 0xb06d1

Reference:
Lunar Lake External Design Specification Volume 1 (734362)

TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage.
	Below prints verified on Lunar Lake RVP board (lnlrvp).
	[DEBUG]  MCH: device id 6410 (rev 02) is LunarLake M

Change-Id: I976d7f269485633d835d204afa224736d71baaa8
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

src/include/cpu/intel/cpu_ids.h

@@ -81,5 +81,6 @@
 #define CPUID_RAPTORLAKE_J0		0xb06a2
 #define CPUID_RAPTORLAKE_Q0		0xb06a3
 #define CPUID_LUNARLAKE_A0_1		0xb06d0
+#define CPUID_LUNARLAKE_A0_2		0xb06d1
 
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -4292,6 +4292,7 @@
 #define PCI_DID_INTEL_RPL_P_ID_7		0xa70a
 #define PCI_DID_INTEL_RPL_P_ID_8		0xa716
 #define PCI_DID_INTEL_LNL_M_ID			0x6400
+#define PCI_DID_INTEL_LNL_M_ID_1		0x6410
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22

src/soc/intel/common/block/cpu/mp_init.c

@@ -33,6 +33,7 @@ static struct device_operations cpu_dev_ops = {
 
 static const struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
+	{ X86_VENDOR_INTEL, CPUID_LUNARLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK },
 	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK },

src/soc/intel/common/block/systemagent/systemagent.c

@@ -415,6 +415,7 @@ struct device_operations systemagent_ops = {
 
 static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_LNL_M_ID,
+	PCI_DID_INTEL_LNL_M_ID_1,
 	PCI_DID_INTEL_MTL_M_ID,
 	PCI_DID_INTEL_MTL_P_ID_1,
 	PCI_DID_INTEL_MTL_P_ID_2,