From 256918bd6d5977be4c020fafec0ba4401e806e25 Mon Sep 17 00:00:00 2001 From: Jan Samek Date: Thu, 19 Jan 2023 14:17:44 +0100 Subject: [PATCH] mb/siemens/mc_apl1/var/mc_apl6: Enable early POST Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl6 and observe that POST codes are displayed before DRAM training. Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728 Signed-off-by: Jan Samek Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- .../siemens/mc_apl1/variants/mc_apl6/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index 146e030dfc..cfda25a75c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_DISABLE_POWER_LIMITS select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM + select NC_FPGA_POST_CODE select TPM_ON_FAST_SPI select TPM_MEASURED_BOOT select HAS_RECOVERY_MRC_CACHE @@ -26,4 +27,19 @@ config VBOOT config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd" +config EARLY_PCI_BRIDGE_DEVICE + hex + depends on NC_FPGA_POST_CODE + default 0x13 + +config EARLY_PCI_BRIDGE_FUNCTION + hex + depends on NC_FPGA_POST_CODE + default 0x3 + +config EARLY_PCI_MMIO_BASE + hex + depends on NC_FPGA_POST_CODE + default 0xfe800000 + endif # BOARD_SIEMENS_MC_APL6