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mb/google/rex/var/deku: Refactor SSD power sequencing

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Improve SSD readiness time by enabling earlier power sequencing.

Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST

The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:

bootblock (A20/0, A19/1)
|
v
romstage (A20/1)

Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.

TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.

Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-02-20 20:19:13 +05:30
parent 9305ccada1
commit 259fc2b119
1 changed files with 6 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/rex/variants/deku/gpio.c
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@@ -38,10 +38,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* GPP_A18 : net NC is not present in the given design */ /* GPP_A18 : net NC is not present in the given design */
PAD_NC(GPP_A18, NONE), PAD_NC(GPP_A18, NONE),
/* GPP_A19 : [] ==> EN_PWR_SSD_OD */
PAD_CFG_GPO(GPP_A19, 1, DEEP),
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO_LOCK(GPP_A20, 1, LOCK_CONFIG),
/* GPP_A21 : [] ==> SOC_GPP_A21 */ /* GPP_A21 : [] ==> SOC_GPP_A21 */
PAD_NC(GPP_A21, NONE), PAD_NC(GPP_A21, NONE),
@@ -395,17 +391,20 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
/* GPP_H10 : [] ==> SOC_WP_OD */ /* GPP_H10 : [] ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG),
/* GPP_A19 : [] ==> EN_PP3300_SSD */
PAD_CFG_GPO(GPP_A19, 1, DEEP),
}; };
static const struct pad_config romstage_gpio_table[] = { static const struct pad_config romstage_gpio_table[] = {
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),
/* GPP_C13 : [] ==> LAN0_PERST_L */ /* GPP_C13 : [] ==> LAN0_PERST_L */
PAD_CFG_GPO(GPP_C13, 0, DEEP), PAD_CFG_GPO(GPP_C13, 0, DEEP),
/* GPP_D02 : [] ==> LAN1_PERST_L */ /* GPP_D02 : [] ==> LAN1_PERST_L */
PAD_CFG_GPO(GPP_D02, 0, DEEP), PAD_CFG_GPO(GPP_D02, 0, DEEP),
/* GPP_A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 1, DEEP),
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)