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Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT

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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M

Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton

Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
2017-10-15 15:06:48 -06:00
committed by Martin Roth
parent f6af8943e2
commit 264566c177
72 changed files with 0 additions and 7118 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/Makefile.inc
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@@ -7,7 +7,6 @@ subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023
@@ -15,7 +14,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370

23
src/cpu/intel/ep80579/Kconfig
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@@ -1,23 +0,0 @@
config CPU_INTEL_EP80579
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE
select SUPPORT_CPU_UCODE_IN_CBFS
if CPU_INTEL_EP80579
# These are just dummy values to keep build happy.
# This CPU does not have tested cache_as_ram.inc.
config DCACHE_RAM_BASE
hex
default 0xfefc0000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif

8
src/cpu/intel/ep80579/Makefile.inc
View File

@@ -1,8 +0,0 @@
ramstage-y += ep80579.c
ramstage-y += ep80579_init.c
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode

20
src/cpu/intel/ep80579/ep80579.c
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@@ -1,20 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
struct chip_operations cpu_intel_ep80579_ops = {
CHIP_NAME("EP80579 CPU")
};

53
src/cpu/intel/ep80579/ep80579_init.c
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@@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Arastra, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
static void ep80579_init(struct device *dev)
{
/* Turn on caching if we haven't already */
x86_enable_cache();
x86_setup_mtrrs();
x86_mtrr_check();
/* Update the microcode */
intel_update_microcode_from_cbfs();
/* Enable the local CPU APICs */
setup_lapic();
};
static struct device_operations cpu_dev_ops = {
.init = ep80579_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x10650 }, /* EP80579 */
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

20
src/cpu/intel/socket_mPGA479M/Kconfig
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@@ -1,20 +0,0 @@
config CPU_INTEL_SOCKET_MPGA479M
bool
select CPU_INTEL_MODEL_69X
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6DX
select CPU_INTEL_MODEL_F2X
select MMX
select SSE
if CPU_INTEL_SOCKET_MPGA479M
config DCACHE_RAM_BASE
hex
default 0xc8000
config DCACHE_RAM_SIZE
hex
default 0x08000
endif

13
src/cpu/intel/socket_mPGA479M/Makefile.inc
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@@ -1,13 +0,0 @@
subdirs-y += ../model_69x
subdirs-y += ../model_6dx
subdirs-y += ../model_f2x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage_legacy.c