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cpu/x86/mtrr: move cache_ramstage() to its only user

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The Intel i3100 northbridge code is the only user of
cache_ramstage(). Therefore, place it next to the sole
consumer.

Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14097
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin
2016-03-15 09:05:54 -05:00
parent 94534b3132
commit 264bf0b27e
2 changed files with 9 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/x86/mtrr/earlymtrr.c
View File

@@ -20,14 +20,6 @@ void set_var_mtrr(
}
#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
static void cache_ramstage(void)
{
/* Enable caching for lower 1MB and ram stage using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
}
const int addr_det = 0;
/* the fixed and variable MTRRs are power-up with random values,

10
src/northbridge/intel/i3100/raminit.c
View File

@@ -926,6 +926,13 @@ static void set_receive_enable(const struct mem_controller *ctrl)
write32(MCBAR+0x154, recenb);
}
static void cache_ramstage(void)
{
/* Enable caching for lower 1MB and ram stage using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
}
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
@@ -1189,7 +1196,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
#if !CONFIG_CACHE_AS_RAM
if (!IS_ENABLED(CONFIG_CACHE_AS_RAM))
cache_ramstage();
#endif
}