soc/amd: factor out acpi_add_fsp_tables

Factor out acpi_add_fsp_tables from the soc_acpi_write_tables function
and move the remaining parts of the soc_acpi_write_tables function to
the SoC's acpi.c. This aligns the other family 17h/19h SoCs more with
Genoa and only leaves the FSP-specific code in agesa_acpi.c which will
be made common in a following patch. I decided against also renaming
agesa_acpi.c to acpi_fsp.c, since that would have made the diff less
readable and the files get deleted in a following patch anyway.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia87ac0e77c5e673e694703b85a4bab85a34b980e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/phoenix/acpi.c

@@ -16,6 +16,7 @@
 #include <arch/smp/mpspec.h>
 #include <console/console.h>
 #include <cpu/amd/cpuid.h>
+#include <device/device.h>
 #include <soc/iomap.h>
 #include <types.h>
 #include "chip.h"
@@ -57,6 +58,19 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
 }
 
+unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
+				    acpi_rsdp_t *rsdp)
+{
+	/* TODO: look into adding CRAT */
+
+	/* IVRS */
+	current = acpi_add_ivrs_table(current, rsdp);
+
+	current = acpi_add_fsp_tables(current, rsdp);
+
+	return current;
+}
+
 const acpi_cstate_t cstate_cfg_table[] = {
 	[0] = {
 		.ctype = 1,