nb/intel/raminit (native): Read PCI mmio size from devicetree

Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.

Tested on Sandybridge Lenovo T520.

Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/apple/macbookair4_2/devicetree.cb

@@ -30,6 +30,9 @@ chip northbridge/intel/sandybridge
 			end
 		end
 	end
+
+	register "pci_mmio_size" = "2048"
+
 	device domain 0x0 on
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"

src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb

@@ -19,6 +19,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		subsystemid 0x1458 0x5000 inherit
 		device pci 00.0 on # host bridge

src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb

@@ -18,6 +18,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		subsystemid 0x1458 0x5000 inherit
 		device pci 00.0 on # host bridge

src/mainboard/google/stout/devicetree.cb

@@ -42,6 +42,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		subsystemid 0x1ae0 0xc000 inherit
 		device pci 00.0 on end # host bridge

src/mainboard/lenovo/t400/devicetree.cb

@@ -23,6 +23,8 @@ chip northbridge/intel/gm45
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x20e0

src/mainboard/lenovo/t420/devicetree.cb

@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21ce

src/mainboard/lenovo/t420s/devicetree.cb

@@ -35,6 +35,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21d2

src/mainboard/lenovo/t430s/devicetree.cb

@@ -35,6 +35,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21fb

src/mainboard/lenovo/t520/devicetree.cb

@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M]

src/mainboard/lenovo/t530/devicetree.cb

@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 01.0 on end # PCIe Bridge for discrete graphics

src/mainboard/lenovo/x200/devicetree.cb

@@ -28,6 +28,8 @@ chip northbridge/intel/gm45
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x20e0

src/mainboard/lenovo/x201/devicetree.cb

@@ -80,6 +80,8 @@ chip northbridge/intel/nehalem
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on # Host bridge
 			subsystemid 0x17aa 0x2193

src/mainboard/lenovo/x220/devicetree.cb

@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21db

src/mainboard/lenovo/x230/devicetree.cb

@@ -36,6 +36,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		device pci 00.0 on
 			subsystemid 0x17aa 0x21fa

src/mainboard/packardbell/ms2290/devicetree.cb

@@ -42,6 +42,8 @@ chip northbridge/intel/nehalem
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		device pci 00.0 on # Host bridge
 			subsystemid 0x1025 0x0379

src/mainboard/roda/rk9/devicetree.cb

@@ -19,6 +19,8 @@ chip northbridge/intel/gm45
 		end
 	end
 
+	register "pci_mmio_size" = "2048"
+
 	device domain 0 on
 		subsystemid 0x4352 0x8986
 		device pci 00.0 on end # host bridge

src/mainboard/samsung/lumpy/devicetree.cb

@@ -34,6 +34,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		ioapic_irq 4 INTA 0x10
 		ioapic_irq 4 INTB 0x11

src/mainboard/samsung/stumpy/devicetree.cb

@@ -32,6 +32,8 @@ chip northbridge/intel/sandybridge
 		end
 	end
 
+	register "pci_mmio_size" = "1024"
+
 	device domain 0 on
 		subsystemid 0x1ae0 0xc000 inherit
 		device pci 00.0 on end # host bridge