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nb/intel/raminit (native): Read PCI mmio size from devicetree

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Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.

Tested on Sandybridge Lenovo T520.

Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Patrick Rudolph
2016-06-09 18:13:34 +02:00
committed by Martin Roth
parent e7f35cd292
commit 266a1f794d
24 changed files with 120 additions and 3 deletions
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24
src/northbridge/intel/gm45/raminit.c
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@@ -20,11 +20,13 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <device/device.h>
#include <spd.h>
#include <console/console.h>
#include <lib.h>
#include "delay.h"
#include "gm45.h"
#include "chip.h"
static const gmch_gfx_t gmch_gfx_types[][5] = {
/* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */
@@ -1156,6 +1158,25 @@ static void vc1_program_timings(const fsb_clock_t fsb)
EPBAR32(0x3c) = timings_by_fsb[fsb][1];
}
#define DEFAULT_PCI_MMIO_SIZE 2048
#define HOST_BRIDGE PCI_DEVFN(0, 0)
static unsigned int get_mmio_size(void)
{
const struct device *dev;
const struct northbridge_intel_gm45_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->pci_mmio_size == 0)
return DEFAULT_PCI_MMIO_SIZE;
else
return cfg->pci_mmio_size;
}
/* @prejedec if not zero, set rank size to 128MB and page size to 4KB. */
static void program_memory_map(const dimminfo_t *const dimms, const channel_mode_t mode, const int prejedec, u16 ggc)
{
@@ -1226,7 +1247,8 @@ static void program_memory_map(const dimminfo_t *const dimms, const channel_mode
}
}
const unsigned int MMIOstart = 0x0c00 + uma_sizem; /* 3GB, makes MTRR configuration small. */
const unsigned int mmio_size = get_mmio_size();
const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem;
const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff;
const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32;
const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE;