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soc/amd: factor out legacy I/O and cf9 decode enable functions

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Replace sb prefix with fch prefix, since those are all FCHs and no south
bridges any more. Verstage on PSP uses the I/O access mechanism instead
of the MMIO one, so keep a separate function for that, but also move it
to the common mmio_util file to have them all in one place.

Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2020-12-08 00:40:04 +01:00
parent 240f99c1c3
commit 26935d1ecc
7 changed files with 24 additions and 39 deletions
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18
src/soc/amd/stoneyridge/southbridge.c
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@@ -200,20 +200,6 @@ static void sb_lpc_decode(void)
lpc_enable_decode(tmp);
}
static void sb_enable_cf9_io(void)
{
uint32_t reg = pm_read32(PM_DECODE_EN);
pm_write32(PM_DECODE_EN, reg | CF9_IO_EN);
}
static void sb_enable_legacy_io(void)
{
uint32_t reg = pm_read32(PM_DECODE_EN);
pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
}
void sb_clk_output_48Mhz(u32 osc)
{
u32 ctrl;
@@ -347,14 +333,14 @@ void bootblock_fch_early_init(void)
sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
enable_acpimmio_decode_pm04();
fch_smbus_init();
sb_enable_cf9_io();
fch_enable_cf9_io();
setup_spread_spectrum(&reboot);
setup_misc(&reboot);
if (reboot)
warm_reset();
sb_enable_legacy_io();
fch_enable_legacy_io();
enable_aoac_devices();
}