sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/baytrail,broadwell: Move stage cache support function

Browse Source 
Let garbage-collection take care of stage_cache_external_region()
when it is not needed and move implementation to a suitable file
already building for needed stages.

Change-Id: Ia6adcc0c8bf6d4abc095ac669aaae876b33ed0f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34669
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-02 06:13:22 +03:00
committed by Martin Roth
parent 825646e643
commit 26a682c944
6 changed files with 30 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/baytrail/Makefile.inc
View File

@@ -13,7 +13,6 @@ romstage-y += iosf.c
romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += spi.c
romstage-y += stage_cache.c
romstage-y += tsc_freq.c
postcar-y += iosf.c
@@ -45,7 +44,6 @@ ramstage-y += sd.c
ramstage-y += smm.c
ramstage-y += southcluster.c
ramstage-y += spi.c
ramstage-y += stage_cache.c
ramstage-y += tsc_freq.c
ramstage-y += xhci.c
ramstage-$(CONFIG_ELOG) += elog.c

14
src/soc/intel/baytrail/memmap.c
View File

@@ -14,6 +14,7 @@
*/
#include <cbmem.h>
#include <stage_cache.h>
#include <soc/iosf.h>
#include <soc/smm.h>
@@ -26,3 +27,16 @@ void *cbmem_top(void)
{
return (void *) smm_region_start();
}
void stage_cache_external_region(void **base, size_t *size)
{
char *smm_base;
/* 1MiB cache size */
const long cache_size = CONFIG_SMM_RESERVED_SIZE;
/* Ramstage cache lives in TSEG region which is the definition of
* cbmem_top(). */
smm_base = cbmem_top();
*size = cache_size;
*base = &smm_base[smm_region_size() - cache_size];
}

31
src/soc/intel/baytrail/stage_cache.c
View File

@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <stage_cache.h>
#include <soc/smm.h>
void stage_cache_external_region(void **base, size_t *size)
{
char *smm_base;
/* 1MiB cache size */
const long cache_size = CONFIG_SMM_RESERVED_SIZE;
/* Ramstage cache lives in TSEG region which is the definition of
* cbmem_top(). */
smm_base = cbmem_top();
*size = cache_size;
*base = &smm_base[smm_region_size() - cache_size];
}

3
src/soc/intel/broadwell/Makefile.inc
View File

@@ -68,9 +68,6 @@ romstage-y += spi.c
postcar-y += spi.c
ramstage-y += spi.c
smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
ramstage-y += stage_cache.c
romstage-y += stage_cache.c
postcar-y += stage_cache.c
ramstage-y += systemagent.c
bootblock-y += tsc_freq.c
ramstage-y += tsc_freq.c

17
src/soc/intel/broadwell/memmap.c
View File

@@ -15,11 +15,14 @@
#define __SIMPLE_DEVICE__
#include <device/pci_ops.h>
#include <cbmem.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
#include <soc/smm.h>
#include <stage_cache.h>
#include <stdint.h>
static uintptr_t dpr_region_start(void)
{
@@ -42,3 +45,15 @@ void *cbmem_top(void)
{
return (void *) dpr_region_start();
}
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region.
* The top of RAM is defined to be the TSEG base address. */
u32 offset = smm_region_size();
offset -= CONFIG_IED_REGION_SIZE;
offset -= CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(cbmem_top() + offset);
*size = CONFIG_SMM_RESERVED_SIZE;
}

31
src/soc/intel/broadwell/stage_cache.c
View File

@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cbmem.h>
#include <soc/smm.h>
#include <stage_cache.h>
#include <stdint.h>
void stage_cache_external_region(void **base, size_t *size)
{
/* The ramstage cache lives in the TSEG region.
* The top of RAM is defined to be the TSEG base address. */
u32 offset = smm_region_size();
offset -= CONFIG_IED_REGION_SIZE;
offset -= CONFIG_SMM_RESERVED_SIZE;
*base = (void *)(cbmem_top() + offset);
*size = CONFIG_SMM_RESERVED_SIZE;
}