diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c
index 5c36721ef5..3d1430fbe3 100644
--- a/src/soc/intel/elkhartlake/finalize.c
+++ b/src/soc/intel/elkhartlake/finalize.c
@@ -9,8 +9,10 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
+#include <intelpch/lockdown.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
@@ -47,12 +49,19 @@ static void pch_finalize(void)
 	pmc_clear_pmcon_sts();
 }
 
+static void sa_finalize(void)
+{
+	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
+		sa_lock_pam();
+}
+
 static void soc_finalize(void *unused)
 {
 	printk(BIOS_DEBUG, "Finalizing chipset.\n");
 
 	pch_finalize();
 	apm_control(APM_CNT_FINALIZE);
+	sa_finalize();
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index ae9584c81b..2bf4a51131 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -148,6 +148,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchWriteProtectionEnable[0] = 0;
 		params->PchUnlockGpioPads = 1;
 		params->RtcMemoryLock = 0;
+		params->SkipPamLock = 1;
 	} else {
 		params->PchLockDownGlobalSmi = 1;
 		params->PchLockDownBiosLock = 1;
@@ -155,6 +156,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PchWriteProtectionEnable[0] = 1;
 		params->PchUnlockGpioPads = 0;
 		params->RtcMemoryLock = 1;
+		params->SkipPamLock = 0;
 	}
 
 	/* Disable PAVP */