soc/intel/icelake: Create macros for FSP consumption

1. Modify PCIEXBAR to accomodate Type-C Root Port
2. LPSS device mode selection

Change-Id: Ib7e4bc304f93e4b63ac2d7f194ca441dd96dd943
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29697
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/icelake/Kconfig

@@ -126,6 +126,10 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xc0000000
+
 config CPU_BCLK_MHZ
 	int
 	default 100
@@ -146,6 +150,10 @@ config SOC_INTEL_I2C_DEV_MAX
 	int
 	default 6
 
+config SOC_INTEL_UART_DEV_MAX
+	int
+	default 3
+
 # Clock divider parameters for 115200 baud rate
 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 	hex