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sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor

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Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-12-19 19:10:45 +02:00 committed by Angel Pons
parent 1749b77b23
commit 26e0f4cefc
3 changed files with 8 additions and 19 deletions
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8
src/soc/intel/broadwell/pch/me.c
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@ -28,10 +28,7 @@
#include <soc/rcba.h> #include <soc/rcba.h>
#include <soc/intel/broadwell/pch/chip.h> #include <soc/intel/broadwell/pch/chip.h>
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
/* Path that the BIOS should take based on ME state */ /* Path that the BIOS should take based on ME state */
static const char *me_bios_path_values[] = { static const char *me_bios_path_values[] = {
@ -772,10 +769,9 @@ static int intel_me_extend_valid(struct device *dev)
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */ /* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count); if (CONFIG(CHROMEOS))
#endif chromeos_set_me_hash(extend, count);
return 0; return 0;
} }

11
src/southbridge/intel/bd82x6x/me_common.c
View File

@ -15,6 +15,8 @@
#include "me.h" #include "me.h"
#include "pch.h" #include "pch.h"
#include <vendorcode/google/chromeos/chromeos.h>
/* Path that the BIOS should take based on ME state */ /* Path that the BIOS should take based on ME state */
static const char *const me_bios_path_values[] = { static const char *const me_bios_path_values[] = {
[ME_NORMAL_BIOS_PATH] = "Normal", [ME_NORMAL_BIOS_PATH] = "Normal",
@ -362,10 +364,6 @@ int intel_mei_setup(struct device *dev)
return 0; return 0;
} }
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
/* Read the Extend register hash of ME firmware */ /* Read the Extend register hash of ME firmware */
int intel_me_extend_valid(struct device *dev) int intel_me_extend_valid(struct device *dev)
{ {
@ -405,10 +403,9 @@ int intel_me_extend_valid(struct device *dev)
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */ /* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count); if (CONFIG(CHROMEOS))
#endif chromeos_set_me_hash(extend, count);
return 0; return 0;
} }

8
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -25,10 +25,7 @@
#include "me.h" #include "me.h"
#include "pch.h" #include "pch.h"
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
#include <vendorcode/google/chromeos/gnvs.h>
#endif
/* Path that the BIOS should take based on ME state */ /* Path that the BIOS should take based on ME state */
static const char *const me_bios_path_values[] __unused = { static const char *const me_bios_path_values[] __unused = {
@ -755,10 +752,9 @@ static int intel_me_extend_valid(struct device *dev)
} }
printk(BIOS_DEBUG, "\n"); printk(BIOS_DEBUG, "\n");
#if CONFIG(CHROMEOS)
/* Save hash in NVS for the OS to verify */ /* Save hash in NVS for the OS to verify */
chromeos_set_me_hash(extend, count); if (CONFIG(CHROMEOS))
#endif chromeos_set_me_hash(extend, count);
return 0; return 0;
} }