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src/soc to src/superio: Fix spelling errors

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Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth
2021-10-01 14:53:22 -06:00
committed by Martin Roth
parent 50863daef8
commit 26f97f9532
75 changed files with 91 additions and 91 deletions
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2
src/soc/intel/quark/Kconfig
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@ -222,7 +222,7 @@ config STORAGE_TEST
select COMMONLIB_STORAGE
select SDHCI_CONTROLLER
help
Read block 0 from each parition of the storage device. User
Read block 0 from each partition of the storage device. User
must also enable one or both of COMMONLIB_STORAGE_SD or
COMMONLIB_STORAGE_MMC.

2
src/soc/intel/quark/chip.h
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@ -87,7 +87,7 @@ struct soc_intel_quark_config {
uint8_t DramDensity;
uint8_t tCL; /* DRAM CAS Latency in clocks */
/* ECC scrub interval in miliseconds 1..255 (0 works as feature
/* ECC scrub interval in milliseconds 1..255 (0 works as feature
* disable)
*/
uint8_t EccScrubInterval;

4
src/soc/intel/quark/include/soc/QuarkNcSocId.h
View File

@ -55,7 +55,7 @@
//
//
// DEVICE 0 (Memroy Controller Hub)
// DEVICE 0 (Memory Controller Hub)
//
#define MC_BUS PCI_BUS_NUMBER_QNC
#define MC_DEV 0x00
@ -729,7 +729,7 @@
#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset
#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable
#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable
#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable
#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable
#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State

2
src/soc/intel/quark/reg_access.c
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@ -69,7 +69,7 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
{
uint32_t offset;
/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
/* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */
if (index == MTRR_CAP_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
else if (index == MTRR_DEF_TYPE_MSR)

2
src/soc/intel/quark/spi_debug.c
View File

@ -79,7 +79,7 @@ void spi_display(volatile struct flash_ctrlr *ctrlr)
printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
/* Display the protection ranges */
printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n");
printk(BIOS_DEBUG, "BIOS Protected Range Registers\n");
for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
status = ctrlr->pbr[index];
printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n",