src/soc to src/superio: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/fch.c

@@ -127,7 +127,7 @@ static void fch_init_resets(void)
 	pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
 }
 
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
 	const struct soc_amd_cezanne_config *cfg = config_of_soc();

src/soc/amd/picasso/acpi/sb_pci0_fch.asl

@@ -29,7 +29,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */

src/soc/amd/picasso/chip.h

@@ -22,7 +22,7 @@ struct __packed usb2_phy_tune {
 	uint8_t	sq_rx_tune;
 	/* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
 	uint8_t	tx_fsls_tune;
-	/* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
+	/* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */
 	uint8_t	tx_pre_emp_amp_tune;
 	/* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
 	uint8_t	tx_pre_emp_pulse_tune;
@@ -99,7 +99,7 @@ struct soc_amd_picasso_config {
 	 * If sb_reset_i2c_peripherals() is called, this devicetree register
 	 * defines which I2C SCL will be toggled 9 times at 100 KHz.
 	 * For example, should we need I2C0 and  I2C3 have their peripheral
-	 * devices reseted by toggling SCL, use:
+	 * devices reset by toggling SCL, use:
 	 *
 	 * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
 	 */

src/soc/amd/picasso/fch.c

@@ -175,7 +175,7 @@ static void al2ahb_clock_gate(void)
 	write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
 }
 
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */
+/* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
 	const struct soc_amd_picasso_config *cfg = config_of_soc();

src/soc/amd/picasso/include/soc/platform_descriptors.h

@@ -7,7 +7,7 @@
 #include <platform_descriptors.h>
 #include <FspsUpd.h>
 
-/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG.
+/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG.
  * TODO: Remove when official definitions arrive. */
 #define SD_DISABLE		0
 #define SD_LOW_SPEED		1

src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl

@@ -56,7 +56,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */

src/soc/amd/stoneyridge/chip.h

@@ -46,7 +46,7 @@ struct soc_amd_stoneyridge_config {
 	 * If sb_reset_i2c_peripherals() is called, this devicetree register
 	 * defines which I2C SCL will be toggled 9 times at 100 KHz.
 	 * For example, should we need I2C0 and  I2C3 have their peripheral
-	 * devices reseted by toggling SCL, use:
+	 * devices reset by toggling SCL, use:
 	 *
 	 * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL)
 	 */

src/soc/amd/stoneyridge/northbridge.c

@@ -400,19 +400,19 @@ void domain_read_resources(struct device *dev)
 	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
 
 	/*
-	 * 0x100000 (1MiB) -> low top useable RAM
+	 * 0x100000 (1MiB) -> low top usable RAM
 	 * cbmem_top() accounts for low UMA and TSEG if they are used.
 	 */
 	ram_resource(dev, idx++, (1 * MiB) / KiB,
 			(mem_useable - (1 * MiB)) / KiB);
 
-	/* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */
+	/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
 	reserved_ram_resource(dev, idx++, mem_useable / KiB,
 					(tom.lo - mem_useable) / KiB);
 
 	/* If there is memory above 4GiB */
 	if (high_tom.hi) {
-		/* 4GiB -> high top useable */
+		/* 4GiB -> high top usable */
 		if (uma_base >= (4ull * GiB))
 			high_mem_useable = uma_base;
 		else
@@ -422,7 +422,7 @@ void domain_read_resources(struct device *dev)
 		ram_resource(dev, idx++, (4ull * GiB) / KiB,
 				((high_mem_useable - (4ull * GiB)) / KiB));
 
-		/* High top useable RAM -> high top RAM */
+		/* High top usable RAM -> high top RAM */
 		if (uma_base >= (4ull * GiB)) {
 			reserved_ram_resource(dev, idx++, uma_base / KiB,
 						uma_size / KiB);

src/soc/cavium/cn81xx/bootblock_custom.S

@@ -130,7 +130,7 @@ ENTRY(_setup_car)
 thunder1_cache_setup:
    /**
     * Setup L2 cache to allow secure access to all of the address space
-    * thunder1 compability list:
+    * thunder1 compatibility list:
     * - CN81XX
     * - CN83XX
     * - CN88XX

src/soc/intel/alderlake/acpi/tcss.asl

@@ -511,7 +511,7 @@ Scope (\_SB.PCI0)
 		TACK, 1,          /* [16:16] IOM Acknowledge bit */
 		DPOF, 1,          /* [17:17] Set 1 to indicate IOM, all the */
 				  /* display is OFF, clear otherwise */
-		Offset(0x70),     /* Pyhsical addr is offset 0x70. */
+		Offset(0x70),     /* Physical addr is offset 0x70. */
 		IMCD, 32,         /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
 		IMDA, 32          /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
 	}

src/soc/intel/apollolake/acpi/northbridge.asl

@@ -18,7 +18,7 @@ Device (MCHC)
 		Offset(0xB4),
 		BGSM,   32,	/* Base of Graphics Stolen Memory */
 		Offset(0xBC),
-		TLUD,   32,	/* Top of Low Useable DRAM */
+		TLUD,   32,	/* Top of Low Usable DRAM */
 	}
 }
 
@@ -58,7 +58,7 @@ Method (_CRS, 0, Serialized)
 		 * PCI MMIO Region (TOLUD - PCI extended base MMCONF)
 		 * This assumes that MMCONF is placed after PCI config space,
 		 * and that no resources are allocated after the MMCONF region.
-		 * This works, sicne MMCONF is hardcoded to 0xe00000000.
+		 * This works, since MMCONF is hardcoded to 0xe00000000.
 		 */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				NonCacheable, ReadWrite,

src/soc/intel/apollolake/romstage.c

@@ -119,7 +119,7 @@ static bool punit_init(void)
 
 	/*
 	 * Poll for bit 8 to check if PCODE has completed its action
-	 * in reponse to BIOS Reset complete.
+	 * in response to BIOS Reset complete.
 	 * We wait here till 1 ms for the bit to get set.
 	 */
 	stopwatch_init_msecs_expire(&sw, 1);

src/soc/intel/baytrail/Kconfig

@@ -136,7 +136,7 @@ config HAVE_REFCODE_BLOB
 	bool "Use a binary refcode blob instead of native ModPHY init"
 	default n
 	help
-	 Use the ChromeBook refcode to intitialize high-speed PHYs instead of
+	 Use the ChromeBook refcode to initialize high-speed PHYs instead of
 	 native code.
 
 if HAVE_REFCODE_BLOB

src/soc/intel/braswell/northcluster.c

@@ -93,7 +93,7 @@ static void nc_read_resources(struct device *dev)
 	if (fsp_reserved_memory_area) {
 		fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area);
 	} else {
-		/* If no FSP reserverd area */
+		/* If no FSP reserved area */
 		fsp_res_base_k = tseg_base_k;
 	}
 

src/soc/intel/broadwell/Kconfig

@@ -23,7 +23,7 @@ config BROADWELL_VBOOT_IN_BOOTBLOCK
 	  Broadwell can either start verstage in a separate stage
 	  right after the bootblock has run or it can start it
 	  after romstage for compatibility reasons.
-	  Broadwell however uses a mrc.bin to initialse memory which
+	  Broadwell however uses a mrc.bin to initialize memory which
 	  needs to be located at a fixed offset. Therefore even with
 	  a separate verstage starting after the bootblock that same
 	  binary is used meaning a jump is made from RW to the RO region

src/soc/intel/cannonlake/chip.h

@@ -436,7 +436,7 @@ struct soc_intel_cannonlake_config {
 	 *
 	 * In general descriptor provides option to set default cpu flex ratio.
 	 * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
-	 * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+	 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
 	 *
 	 * Only override CPU flex ratio if don't want to boot with non-turbo max.
 	 */

src/soc/intel/common/Makefile.inc

@@ -41,7 +41,7 @@ MMA_TEST_CONFIG_NAMES = $(notdir $(wildcard $(MMA_BLOBS_PATH)/configs/*))
 #	$(3) is file type, efi for test names (all .EFI files under $(MMA_BLOBS_PATH)/tests )
 #			 , mma for test param (all .BIN files under $(MMA_BLOBS_PATH)/configs/<test name>)
 #
-# $(MMA_BLOBS_PATH)/tests/<testX>.efi has coresponding test params
+# $(MMA_BLOBS_PATH)/tests/<testX>.efi has corresponding test params
 #  at $(MMA_BLOBS_PATH)/configs/<testX>/<XYZ>.bin
 #
 

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -545,7 +545,7 @@ program_sf2:
 
 	/*
 	 * Calculate the SF Mask 1:
-	 * 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0]
+	 * 1. Calculate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0]
 	 * 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2
 	 * 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2
 	 */

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -325,7 +325,7 @@ static void fast_spi_enable_ext_bios(void)
 		       "Only 32MiB windows are supported for extended BIOS!");
 #endif
 
-	/* Confgiure DMI Source decode for Extended BIOS Region */
+	/* Configure DMI Source decode for Extended BIOS Region */
 	if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE,
 				soc_get_spi_dmi_destination_id()) == CB_ERR)
 		return;

src/soc/intel/common/block/include/intelblocks/tcss.h

@@ -130,7 +130,7 @@ enum pmc_ipc_command_type {
 struct tcss_mux_info {
 	bool dp; /* DP connected */
 	bool usb; /* USB connected */
-	bool cable; /* Activ/Passive Cable */
+	bool cable; /* Active/Passive Cable */
 	bool polarity; /* polarity of connected device */
 	bool hpd_lvl; /* HPD Level assert */
 	bool hpd_irq; /* HPD IRQ assert */

src/soc/intel/common/block/pmc/Kconfig

@@ -17,7 +17,7 @@ config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
 	bool
 	help
 	  Select this on platforms where the PMC device is discoverable
-	  when scanning busses.
+	  when scanning buses.
 
 config SOC_INTEL_COMMON_BLOCK_PMC_EPOC
 	bool

src/soc/intel/common/block/usb4/Kconfig

@@ -25,4 +25,4 @@ config SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
 	depends on SOC_INTEL_COMMON_BLOCK_USB4
 	select PCIEXP_HOTPLUG
 	help
-	  Enable USB4 PCIe resources for reserving hotplug busses and memory.
+	  Enable USB4 PCIe resources for reserving hotplug buses and memory.

src/soc/intel/denverton_ns/include/soc/pmc.h

@@ -11,7 +11,7 @@
 #define MASK_PMC_ACPI_BASE 0xfffc
 #define PMC_ACPI_CNT 0x44
 #define PMC_ACPI_CNT_PWRM_EN (1 << 8)			   /* PWRM enable */
-#define PMC_ACPI_CNT_ACPI_EN (1 << 7)			   /* ACPI eanble */
+#define PMC_ACPI_CNT_ACPI_EN (1 << 7)			   /* ACPI enable */
 #define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \
 							      */
 #define PMC_ACPI_CNT_SCIS_MASK 0x07

src/soc/intel/quark/Kconfig

@@ -222,7 +222,7 @@ config STORAGE_TEST
 	select COMMONLIB_STORAGE
 	select SDHCI_CONTROLLER
 	help
-	  Read block 0 from each parition of the storage device.  User
+	  Read block 0 from each partition of the storage device.  User
 	  must also enable one or both of COMMONLIB_STORAGE_SD or
 	  COMMONLIB_STORAGE_MMC.
 

src/soc/intel/quark/chip.h

@@ -87,7 +87,7 @@ struct soc_intel_quark_config {
 	uint8_t  DramDensity;
 	uint8_t  tCL;           /* DRAM CAS Latency in clocks */
 
-	/* ECC scrub interval in miliseconds 1..255 (0 works as feature
+	/* ECC scrub interval in milliseconds 1..255 (0 works as feature
 	 * disable)
 	 */
 	uint8_t EccScrubInterval;

src/soc/intel/quark/include/soc/QuarkNcSocId.h

@@ -55,7 +55,7 @@
 //
 
 //
-// DEVICE 0 (Memroy Controller Hub)
+// DEVICE 0 (Memory Controller Hub)
 //
 #define MC_BUS                  PCI_BUS_NUMBER_QNC
 #define MC_DEV                  0x00
@@ -729,7 +729,7 @@
 #define   V_QNC_PCIE_SLCAP_PSN_OFFSET         19    //Slot number offset
 #define R_QNC_PCIE_SLCTL                    0x58    //~ 59h
 #define   B_QNC_PCIE_SLCTL_HPE                (BIT5)  // Hot plug intr enable
-#define   B_QNC_PCIE_SLCTL_PDE                (BIT3)  // Presense detect enable
+#define   B_QNC_PCIE_SLCTL_PDE                (BIT3)  // Presence detect enable
 #define   B_QNC_PCIE_SLCTL_ABE                (BIT0)  // Attn Btn Pressed Enable
 #define R_QNC_PCIE_SLSTS                    0x5A    //~ 5Bh
 #define   B_QNC_PCIE_SLSTS_PDS                (BIT6)  // Present Detect State

src/soc/intel/quark/reg_access.c

@@ -69,7 +69,7 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
 {
 	uint32_t offset;
 
-	/* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
+	/* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */
 	if (index == MTRR_CAP_MSR)
 		offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
 	else if (index == MTRR_DEF_TYPE_MSR)

src/soc/intel/quark/spi_debug.c

@@ -79,7 +79,7 @@ void spi_display(volatile struct flash_ctrlr *ctrlr)
 	printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
 
 	/* Display the protection ranges */
-	printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n");
+	printk(BIOS_DEBUG, "BIOS Protected Range Registers\n");
 	for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
 		status = ctrlr->pbr[index];
 		printk(BIOS_DEBUG, "  %d: 0x%08x: 0x%08x - 0x%08x %s\n",

src/soc/intel/skylake/acpi.c

@@ -36,7 +36,7 @@
 #define  CPUID_6_EAX_ISST	(1 << 7)
 
 /*
- * List of suported C-states in this processor.
+ * List of supported C-states in this processor.
  */
 enum {
 	C_STATE_C0,		/* 0 */

src/soc/intel/skylake/include/soc/nhlt.h

@@ -30,7 +30,7 @@ enum {
 int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);
 
 /*
- * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0
+ * Add nau88l25 headset codec on provided SSP link. Return 0 on success, < 0
  * on error.
  */
 int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink);

src/soc/intel/tigerlake/acpi/tcss.asl

@@ -511,7 +511,7 @@ Scope (\_SB.PCI0)
 		TACK, 1,          /* [16:16] IOM Acknowledge bit */
 		DPOF, 1,          /* [17:17] Set 1 to indicate IOM, all the */
 				  /* display is OFF, clear otherwise */
-		Offset(0x70),     /* Pyhsical addr is offset 0x70. */
+		Offset(0x70),     /* Physical addr is offset 0x70. */
 		IMCD, 32,         /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
 		IMDA, 32          /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
 	}

src/soc/intel/xeon_sp/util.c

@@ -168,7 +168,7 @@ void xeonsp_init_cpu_config(void)
 	unsigned int num_sockets;
 
 	/*
-	 * sort APIC ids in asending order to identify apicid ranges for
+	 * sort APIC ids in ascending order to identify apicid ranges for
 	 * each numa domain
 	 */
 	for (dev = all_devices; dev; dev = dev->next) {

src/soc/mediatek/common/include/soc/eint_event.h

@@ -6,7 +6,7 @@
 #include <device/mmio.h>
 #include <soc/addressmap.h>
 
-/* eint event mask cler register */
+/* eint event mask clear register */
 struct eint_event_reg {
 	uint32_t eint_event_mask_clr[7];
 };

src/soc/mediatek/common/mmu_operations.c

@@ -50,6 +50,6 @@ void mtk_mmu_disable_l2c_sram(void)
 
 	mtk_soc_disable_l2c_sram();
 
-	/* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
+	/* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */
 	mmu_enable();
 }

src/soc/mediatek/mt8173/dramc_pi_basic_api.c

@@ -777,7 +777,7 @@ u32 dramc_engine2(u32 channel, enum dram_tw_op wr, u32 test2_1, u32 test2_2,
 	 * ISI              0 | 0
 	 * AUD              0 | 1
 	 * XTALK            1 | 0
-	 * UNKNOW           1 | 1
+	 * UNKNOWN          1 | 1
 	 */
 	switch (testaudpat) {
 	case XTALK:

src/soc/mediatek/mt8192/pll.c

@@ -524,7 +524,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
 		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
 				CLK_MISC_CFG_0_METER_DIV, 0);
 	} else {
-		die("unsupport fmeter type\n");
+		die("unsupported fmeter type\n");
 	}
 
 	/* enable frequency meter */

src/soc/mediatek/mt8195/pll.c

@@ -844,7 +844,7 @@ u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
 		SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0,
 				CLK_MISC_CFG_0_METER_DIV, 0);
 	} else {
-		die("unsupport fmeter type\n");
+		die("unsupported fmeter type\n");
 	}
 
 	/* enable frequency meter */

src/soc/nvidia/tegra124/chip.h

@@ -54,7 +54,7 @@ struct soc_nvidia_tegra124_config {
 	/* Delay before from power on asserting vdd */
 	int vdd_delay_ms;
 
-	/* Delay beween pwm and backlight_en_gpio is asserted */
+	/* Delay between pwm and backlight_en_gpio is asserted */
 	int pwm_to_bl_delay_ms;
 
 	/* Delay before HPD high */

src/soc/nvidia/tegra124/dp.c

@@ -465,7 +465,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
 	return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED;
 }
 
-/* Calcuate if given cfg can meet the mode request. */
+/* Calculate if given cfg can meet the mode request. */
 /* Return true if mode is possible, false otherwise. */
 static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 	const struct soc_nvidia_tegra124_config *config,

src/soc/nvidia/tegra210/Kconfig

@@ -79,7 +79,7 @@ config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS
 	default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
 	default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
 	help
-	  Map the UART names to the respective MMIO addres.
+	  Map the UART names to the respective MMIO addresses.
 
 config BOOTROM_SDRAM_INIT
 	bool "SoC BootROM does SDRAM init with full BCT"

src/soc/nvidia/tegra210/Makefile.inc

@@ -137,7 +137,7 @@ req_tz_size=$(shell expr $(ttb_size) + $(sec_size))
 tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB))
 
 ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1)
-     $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
+     $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB")
 endif
 
 # BL31 component is placed towards the end of 32-bit address space. This assumes

src/soc/nvidia/tegra210/dp.c

@@ -477,7 +477,7 @@ static int _tegra_dp_lower_link_config(struct tegra_dc_dp_data *dp,
 	return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED;
 }
 
-/* Calcuate if given cfg can meet the mode request. */
+/* Calculate if given cfg can meet the mode request. */
 /* Return true if mode is possible, false otherwise. */
 static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
 	const struct soc_nvidia_tegra210_config *config,

src/soc/nvidia/tegra210/include/soc/addressmap.h

@@ -94,7 +94,7 @@ enum {
 /* Return total size of DRAM memory configured on the platform. */
 int sdram_size_mb(void);
 
-/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */
+/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */
 void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
 void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
 

src/soc/nvidia/tegra210/mipi_dsi.c

@@ -193,7 +193,7 @@ ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,
 		/*
 		 * DCS long write packets contain the word count in the header
 		 * bytes 1 and 2 and have a payload containing the DCS command
-		 * byte folowed by word count minus one bytes.
+		 * byte followed by word count minus one bytes.
 		 *
 		 * DCS short write packets encode the DCS command and up to
 		 * one parameter in header bytes 1 and 2.

src/soc/nvidia/tegra210/sdram.c

@@ -155,7 +155,7 @@ static void sdram_set_pad_macros(const struct sdram_params *param,
 
 	/*
 	 * Program CMD mapping. Required before brick mapping, else
-	 * we can't gaurantee CK will be differential at all times.
+	 * we can't guarantee CK will be differential at all times.
 	 */
 	write32(&regs->fbio_cfg7, param->EmcFbioCfg7);
 
@@ -979,7 +979,7 @@ static void sdram_set_refresh(const struct sdram_params *param,
 
 	/* Enable EMC pipe clock gating */
 	write32(&regs->cfg_pipe_clk, param->EmcCfgPipeClk);
-	/* Depending on freqency, enable CMD/CLK fdpd */
+	/* Depending on frequency, enable CMD/CLK fdpd */
 	write32(&regs->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp);
 }
 

src/soc/qualcomm/ipq40xx/gpio.c

@@ -18,7 +18,7 @@ static inline int gpio_not_valid(gpio_t gpio)
 }
 
 /*******************************************************
-Function description: configure GPIO functinality
+Function description: configure GPIO functionality
 Arguments :
 gpio_t gpio - Gpio number
 unsigned func - Functionality number
@@ -77,7 +77,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
 }
 
 /*******************************************************
-Function description: get GPIO IO functinality details
+Function description: get GPIO IO functionality details
 Arguments :
 gpio_t gpio - Gpio number
 unsigned *in - Value of GPIO input

src/soc/qualcomm/ipq40xx/spi.c

@@ -328,7 +328,7 @@ static unsigned char spi_read_byte(struct ipq_spi_slave *ds)
 }
 
 /*
- * Function to check wheather Input or Output FIFO
+ * Function to check whether Input or Output FIFO
  * has data to be serviced
  */
 static int check_fifo_status(void *reg_addr)
@@ -627,7 +627,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 		|| ((bus == BLSP0_SPI) && (cs > 2))
 		|| ((bus == BLSP1_SPI) && (cs > 0))) {
 		printk(BIOS_ERR,
-			"SPI error: unsupported bus %d (Supported busses 0, 1 and 2) "
+			"SPI error: unsupported bus %d (Supported buses 0, 1 and 2) "
 			"or chipselect\n", bus);
 		return -1;
 	}

src/soc/qualcomm/ipq806x/gpio.c

@@ -18,7 +18,7 @@ static inline int gpio_not_valid(gpio_t gpio)
 }
 
 /*******************************************************
-Function description: configure GPIO functinality
+Function description: configure GPIO functionality
 Arguments :
 gpio_t gpio - Gpio number
 unsigned func - Functionality number
@@ -77,7 +77,7 @@ void gpio_tlmm_config_get(gpio_t gpio, unsigned int *func,
 }
 
 /*******************************************************
-Function description: get GPIO IO functinality details
+Function description: get GPIO IO functionality details
 Arguments :
 gpio_t gpio - Gpio number
 unsigned *in - Value of GPIO input

src/soc/qualcomm/ipq806x/i2c.c

@@ -84,7 +84,7 @@ static int i2c_init(unsigned int bus)
 		qup_config = &gsbi7_qup_config;
 		break;
 	default:
-		printk(BIOS_ERR, "QUP configuration not defind for GSBI%d.\n",
+		printk(BIOS_ERR, "QUP configuration not defined for GSBI%d.\n",
 		       gsbi_id);
 		return 1;
 	}

src/soc/qualcomm/ipq806x/spi.c

@@ -758,7 +758,7 @@ static int spi_ctrlr_setup(const struct spi_slave *slave)
 		|| ((bus == GSBI6_SPI) && (cs > 0))
 		|| ((bus == GSBI7_SPI) && (cs > 0))) {
 		printk(BIOS_ERR, "SPI error: unsupported bus %d "
-			"(Supported busses 0,1 and 2) or chipselect\n", bus);
+			"(Supported buses 0,1 and 2) or chipselect\n", bus);
 	}
 
 	for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) {

src/soc/qualcomm/ipq806x/uart.c

@@ -367,7 +367,7 @@ uint8_t uart_rx_byte(unsigned int idx)
 	return byte;
 }
 
-/* TODO: Implement fuction */
+/* TODO: Implement function */
 void uart_fill_lb(void *data)
 {
 }

src/soc/qualcomm/qcs405/spi.c

@@ -376,7 +376,7 @@ static unsigned char spi_read_byte(struct qcs_spi_slave *ds)
 }
 
 /*
- * Function to check wheather Input or Output FIFO
+ * Function to check whether Input or Output FIFO
  * has data to be serviced
  */
 static int check_fifo_status(void *reg_addr)

src/soc/samsung/exynos5250/dmc_init_ddr3.c

@@ -124,7 +124,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 	if (mem_reset) {
 		/* Send NOP, MRS and ZQINIT commands.
 		 * Sending MRS command will reset the DRAM. We should not be
-		 * reseting the DRAM after resume, this will lead to memory
+		 * resetting the DRAM after resume, this will lead to memory
 		 * corruption as DRAM content is lost after DRAM reset
 		 */
 		dmc_config_mrs(mem, exynos_dmc);

src/soc/samsung/exynos5250/include/soc/gpio.h

@@ -546,7 +546,7 @@ int gpio_set_value(unsigned int gpio, int value);
 enum mvl3 {
 	LOGIC_0,
 	LOGIC_1,
-	LOGIC_Z,		/* high impedence / tri-stated / floating */
+	LOGIC_Z,		/* high impedance / tri-stated / floating */
 };
 
 #endif	/* CPU_SAMSUNG_EXYNOS5250_GPIO_H */

src/soc/samsung/exynos5420/dmc_init_ddr3.c

@@ -147,7 +147,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	if (reset) {
 		/* Send NOP, MRS and ZQINIT commands.
 		 * Sending MRS command will reset the DRAM. We should not be
-		 * reseting the DRAM after resume, this will lead to memory
+		 * resetting the DRAM after resume, this will lead to memory
 		 * corruption as DRAM content is lost after DRAM reset.
 		 */
 		dmc_config_mrs(mem, exynos_drex0);

src/soc/sifive/fu540/ux00ddr.h

@@ -82,14 +82,14 @@ static inline void ux00ddr_mask_mc_init_complete_interrupt(size_t ahbregaddr) {
 
 static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) {
   // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status
-  // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured
+  // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred
-  // Bit [1] A memory access outside the defined PHYSICAL memory space has occured
+  // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred
   _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET));
 }
 
 static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) {
   // Mask off Bit 7 of Interrupt Status
-  // Bit [7] An error occured on the port command channel
+  // Bit [7] An error occurred on the port command channel
   _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET);
 }
 

src/southbridge/amd/agesa/hudson/acpi/fch.asl

@@ -67,7 +67,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */

src/southbridge/amd/cimx/sb800/acpi/fch.asl

@@ -77,7 +77,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */

src/southbridge/amd/pi/hudson/acpi/fch.asl

@@ -50,7 +50,7 @@ Name(CRES, ResourceTemplate() {
 	 * The Secondary bus range for PCI0 lets the system
 	 * know what bus values are allowed on the downstream
 	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
+	 * PCI buses can have 256 secondary buses which
 	 * range from [0-0xFF] but they do not need to be
 	 * sequential.
 	 */

src/southbridge/intel/bd82x6x/azalia.c

@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the Azalia get's a bar above 4G.
+	// NOTE this will break as soon as the Azalia gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);

src/southbridge/intel/bd82x6x/lpc.c

@@ -31,7 +31,7 @@
 typedef struct southbridge_intel_bd82x6x_config config_t;
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */

src/southbridge/intel/i82371eb/acpi_tables.c

@@ -29,7 +29,7 @@ void generate_cpu_entries(const struct device *device)
 	int numcpus = determine_total_number_of_cores();
 	printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
 
-	/* without the outer scope, furhter ssdt addition will end up
+	/* without the outer scope, further ssdt addition will end up
 	 * within the processor statement */
 	acpigen_write_scope("\\_SB");
 	for (cpu=0; cpu < numcpus; cpu++) {

src/southbridge/intel/i82371eb/smbus.c

@@ -27,7 +27,7 @@ static void pwrmgt_enable(struct device *dev)
 	 * bit25 (lid_pol): 1=invert lid polarity
 	 * bit24 (sm_freeze): 1=freeze idle and standby timers
 	 * bit16 (end of smi): 0=disable smi assertion (cleared by hw)
-	 * bits8-15,26: global standby timer inital count 127 * 4minutes
+	 * bits8-15,26: global standby timer initial count 127 * 4minutes
 	 * bit2  (thrm_pol): 1=active low THRM#
 	 * bit0  (smi_en): 1=disable smi generation upon smi event
 	 */

src/southbridge/intel/i82801dx/lpc.c

@@ -32,7 +32,7 @@ static void i82801dx_enable_acpi(struct device *dev)
 }
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */

src/southbridge/intel/i82801gx/azalia.c

@@ -190,7 +190,7 @@ static void azalia_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the Azalia get's a bar above 4G.
+	// NOTE this will break as soon as the Azalia gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base);

src/southbridge/intel/i82801ix/azalia.c

@@ -183,7 +183,7 @@ static void azalia_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the Azalia get's a bar above 4G.
+	// NOTE this will break as soon as the Azalia gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);

src/southbridge/intel/i82801jx/azalia.c

@@ -183,7 +183,7 @@ static void azalia_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the Azalia get's a bar above 4G.
+	// NOTE this will break as soon as the Azalia gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);

src/southbridge/intel/ibexpeak/azalia.c

@@ -162,7 +162,7 @@ static void azalia_init(struct device *dev)
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the Azalia get's a bar above 4G.
+	// NOTE this will break as soon as the Azalia gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "Azalia: base = %p\n", base);

src/southbridge/intel/ibexpeak/lpc.c

@@ -28,7 +28,7 @@
 typedef struct southbridge_intel_ibexpeak_config config_t;
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */

src/southbridge/intel/lynxpoint/lpc.c

@@ -25,7 +25,7 @@
 #define NMI_OFF	0
 
 /**
- * Set miscellanous static southbridge features.
+ * Set miscellaneous static southbridge features.
  *
  * @param dev PCI device with I/O APIC control registers
  */

src/southbridge/intel/lynxpoint/me_status.c

@@ -187,7 +187,7 @@ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2)
 		break;
 
 	default:
-		printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x",
+		printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x",
 		       hfs2->progress_code, hfs2->current_state);
 	}
 	printk(BIOS_DEBUG, "\n");

src/southbridge/intel/lynxpoint/pch.h

@@ -647,7 +647,7 @@ void mainboard_config_rcba(void);
 #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET)
 #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
 
-/* Reigsters within the SPIBAR */
+/* Registers within the SPIBAR */
 #define SSFC 0x91
 #define FDOC 0xb0
 #define FDOD 0xb4

src/superio/acpi/pnp_config.asl

@@ -26,7 +26,7 @@
 Mutex(CONF_MODE_MUTEX, 1)
 
 /*
- * Enter configuration mode (and aquire mutex)
+ * Enter configuration mode (and acquire mutex)
  * Method must be run before accessing the configuration region.
  * Parameter is the LDN which should be accessed. Values >= 0xFF mean
  * no LDN switch should be done.

src/superio/ite/it8772f/it8772f.h

@@ -103,7 +103,7 @@ enum thermal_mode {
 /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */
 #define GPIO_REG_POLARITY(x) (0xb0 + (x))
 
-/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */
+/* GPIO Internal Pull-up: 1: Enable, 0: Disable */
 #define GPIO_REG_PULLUP(x)   (0xb8 + (x))
 
 /* GPIO Function Select: 1: Simple I/O, 0: Alternate function */

src/superio/winbond/w83627hf/acpi/superio.asl

@@ -33,10 +33,10 @@
  * NO_W83627HF_GAME:     don't expose the game port
  * NO_W83627HF_MIDI:     don't expose the MIDI port
  * NO_W83627HF_HWMON:    don't expose the hardware monitor as
- *                       PnP "Motherboard Ressource"
+ *                       PnP "Motherboard Resource"
  * W83627HF_KBC_COMPAT:  show the keyboard controller and the PS/2 mouse as
  *                       enabled if it is disabled but an address is assigned
- *                       to it. This may be neccessary in some cases.
+ *                       to it. This may be necessary in some cases.
  *
  * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0
  * http://www.itox.com/pages/support/wdt/W83627HF.pdf
@@ -115,14 +115,14 @@ Device(SIO) {
 		Offset (0x74),
 		DMA0,	8,	/* DMA */
 		Offset (0xE0),
-		/* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */
+		/* CRE0-CRE4: function logical device dependent, seems to be reserved for ACPI settings */
 		CRE0,	8,
 		CRE1,	8,
 		CRE2,	8,
 		CRE3,	8,
 		CRE4,	8,
 		Offset (0xF0),
-		/* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */
+		/* OPT1-OPTA aka CRF0-CRF9: function logical device dependent */
 		OPT1,	8,
 		OPT2,	8,
 		OPT3,	8,
@@ -143,7 +143,7 @@ Device(SIO) {
 		})
 	}
 
-	/* Enter configuration mode (and aquire mutex)
+	/* Enter configuration mode (and acquire mutex)
 	   Method must be run before accessing the configuration region.
 	   Parameter is the LDN which should be accessed. Values >= 0xFF mean
 	   no LDN switch should be done.