From 2721846dab2c5e7a207e985cb634588f380744bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Philipp=20Gro=C3=9F?= Date: Thu, 6 Jun 2024 13:12:11 +0200 Subject: [PATCH] mb/asrock: Add Fatal1ty Z87 Professional (Haswell) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This port was done via autoport and subsequent manual tweaking. Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM! The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - both RJ-45 Gigabit LAN Ports - USB 2.0 Ports - USB 3.1 Gen1 Ports - both USB 3.1 Gen1 headers - HD Audio Jack (audio output) - all six SATA3 6.0 Gb/s connectors by Intel - all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061 - all three PCI Express 3.0 x16 slots - PCI Express 2.0 x1 slot - half mini-PCI Express slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Front panel audio connector - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266 Signed-off-by: Jan Philipp Groß Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913 Tested-by: build bot (Jenkins) Reviewed-by: Nicholas Chin Reviewed-by: Angel Pons Reviewed-by: Felix Singer --- .../asrock/fatal1ty_z87_professional/Kconfig | 26 +++ .../fatal1ty_z87_professional/Kconfig.name | 3 + .../fatal1ty_z87_professional/Makefile.mk | 6 + .../fatal1ty_z87_professional/acpi/ec.asl | 3 + .../acpi/platform.asl | 10 + .../acpi/superio.asl | 3 + .../fatal1ty_z87_professional/board_info.txt | 7 + .../fatal1ty_z87_professional/bootblock.c | 8 + .../asrock/fatal1ty_z87_professional/data.vbt | Bin 0 -> 6144 bytes .../fatal1ty_z87_professional/devicetree.cb | 133 ++++++++++++ .../asrock/fatal1ty_z87_professional/dsdt.asl | 28 +++ .../gma-mainboard.ads | 17 ++ .../asrock/fatal1ty_z87_professional/gpio.c | 192 ++++++++++++++++++ .../fatal1ty_z87_professional/hda_verb.c | 25 +++ .../fatal1ty_z87_professional/romstage.c | 44 ++++ 15 files changed, 505 insertions(+) create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/Kconfig create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/Kconfig.name create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/acpi/ec.asl create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/acpi/platform.asl create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/acpi/superio.asl create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/board_info.txt create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/data.vbt create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/devicetree.cb create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/dsdt.asl create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/gma-mainboard.ads create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/gpio.c create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c create mode 100644 src/mainboard/asrock/fatal1ty_z87_professional/romstage.c diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig new file mode 100644 index 0000000000..b1600ef42f --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig @@ -0,0 +1,26 @@ +## SPDX-License-Identifier: GPL-2.0-only +if BOARD_ASROCK_FATAL1TY_Z87_PROFESSIONAL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/fatal1ty_z87_professional" + +config MAINBOARD_PART_NUMBER + default "Fatal1ty Z87 Professional" + +config USBDEBUG_HCD_INDEX + default 2 # USB-2.0-Header with the designation USB4_5 +endif diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig.name b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig.name new file mode 100644 index 0000000000..b413e2d5db --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/Kconfig.name @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only +config BOARD_ASROCK_FATAL1TY_Z87_PROFESSIONAL + bool "Fatal1ty Z87 Professional" diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk new file mode 100644 index 0000000000..93f729d787 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/Makefile.mk @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/acpi/ec.asl b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/acpi/platform.asl b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/acpi/superio.asl b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/superio.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/board_info.txt b/src/mainboard/asrock/fatal1ty_z87_professional/board_info.txt new file mode 100644 index 0000000000..d6dfa6bec8 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Fatal1ty%20Z87%20Professional/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c new file mode 100644 index 0000000000..1cec5c4fc0 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/data.vbt b/src/mainboard/asrock/fatal1ty_z87_professional/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..38bf6ea0c9d51f544f0ac72ecc6d8836d39b6d6e GIT binary patch literal 6144 zcmeHJU2GIp6h3!mc6WAmX1X0JY*(nKKww*GJ1wL(O^LJZ7I(`+w?C9hFf6buq6JC; zgFgu?)`&mRjUfaKfhHIuBobZ>FFv3#fdoR(2+y4q`kyu(CUuL{~CkLQ~~px=xnPMDM_wSadMDrZd^wwG@xS zbSMOGT?NQ6HeGFLZf#9$-ku$a^w(j0U?ncwvTox@wkej~_R{t(qnPSSV08WZ>_~QO z?e=U22Zo-BBIneU&K(;^GPr!lrghn|cH~49jm?W17cN3Ho10qNnp(`}g=8;mr~kq> zO^J1P^)5>#lF`9L?{e(z$5>(@Ixx_^tTXv6ruuv1iO$4ecT7`?{pi{<`pVeG4KHlR zNLL-Un5Nl4oXu!A8N0TOjW%L*WCZ(p%r@-LZp)6noXs?93gU;F;J>l z%w>wZI%#WBOu6@iqau!OXMo@tyMI9G&7yHPL(yN-|2#mQ20c_rM7d*prcJv7pzyXP!cI_hKQP_9 z3SRU!K*f9DFAZSn`~RBZw~Jlbbd^;7Trt#Qv9KLghrkk^n6o^74lYmuzTmsg_DuVKT27+MxfTjDTj7#Fm&ePqf^vGc z^G;1Uo>_|^NIRNe7Ce$#`j$*Cw4`X2DsxkiAnJ9MlMYRn~hcPv7b$-KRTP*cju!|RRtiFCNeGSMxuG@4SL z&hRvvIbS)wh;-y8Mo-KkhI;-M05N#-_J*oXc*e_^48 z?D=s2wJEgcLR;G!tl@^+V + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/gma-mainboard.ads b/src/mainboard/asrock/fatal1ty_z87_professional/gma-mainboard.ads new file mode 100644 index 0000000000..61dc90a151 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI2, -- DP + HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/gpio.c b/src/mainboard/asrock/fatal1ty_z87_professional/gpio.c new file mode 100644 index 0000000000..7ecd7bbad4 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c b/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c new file mode 100644 index 0000000000..9c381e650d --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x11020011, /* Codec Vendor / Device ID: Creative */ + 0x18491020, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491020), + AZALIA_PIN_CFG(0, 0x0b, 0x01014010), + AZALIA_PIN_CFG(0, 0x0c, 0x014580f0), + AZALIA_PIN_CFG(0, 0x0d, 0x014570f0), + AZALIA_PIN_CFG(0, 0x0e, 0x01c530f0), + AZALIA_PIN_CFG(0, 0x0f, 0x0221401f), + AZALIA_PIN_CFG(0, 0x10, 0x02216011), + AZALIA_PIN_CFG(0, 0x11, 0x02012014), + AZALIA_PIN_CFG(0, 0x12, 0x37a791f0), + AZALIA_PIN_CFG(0, 0x13, 0x908700f0), + AZALIA_PIN_CFG(0, 0x18, 0x500000f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c new file mode 100644 index 0000000000..44932e7229 --- /dev/null +++ b/src/mainboard/asrock/fatal1ty_z87_professional/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};