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southbridge/intel/lynxpoint: Use common gpio.c

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Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.

Needs test on real hardware !

Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph
2016-02-06 18:07:59 +01:00
committed by Martin Roth
parent 9a4881a783
commit 273a8dca1f
17 changed files with 25 additions and 352 deletions
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24
src/mainboard/intel/baskingridge/chromeos.c
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@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <southbridge/intel/lynxpoint/gpio.h>
#include <southbridge/intel/common/gpio.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -82,38 +82,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
#endif
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
/*
* Developer: GPIO48, Connected to J8E4, however the silkscreen says
* J8E3. The jumper is active low.
*/
return !((gp_lvl2 >> (48-32)) & 1);
return !get_gpio(48);
}
int get_recovery_mode_switch(void)
{
device_t dev;
#ifdef __PRE_RAM__
dev = PCI_DEV(0, 0x1f, 0);
#else
dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
#endif
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
/*
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
return (gp_lvl3 >> (69-64)) & 1;
return get_gpio(69);
}
int get_write_protect_state(void)