mb/google/brya: Remove Pcie Generic driver for WWAN

This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.

Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.

BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/brya/Kconfig

@@ -15,7 +15,6 @@ config BOARD_GOOGLE_BRYA_COMMON
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_SOUNDWIRE
 	select DRIVERS_INTEL_USB4_RETIMER
-	select DRIVERS_PCIE_GENERIC
 	select DRIVERS_SOUNDWIRE_ALC5682
 	select DRIVERS_SOUNDWIRE_MAX98373
 	select DRIVERS_SPI_ACPI

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -147,26 +147,6 @@ chip soc/intel/alderlake
 		device ref i2c3 on end
 		device ref heci1 on end
 		device ref sata on end
-		device ref pcie_rp6 on
-			# Enable WWAN PCIE 6 using clk 5
-			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
-				register "reset_off_delay_ms" = "20"
-				register "srcclk_pin" = "5"
-				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
-				register "skip_on_off_support" = "true"
-				device generic 0 alias rp6_rtd3 on end
-			end
-			register "pch_pcie_rp[PCH_RP(6)]" = "{
-				.clk_src = 5,
-				.clk_req = 5,
-				.flags = PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-			chip drivers/pcie/generic
-				register "is_untrusted" = "1"
-				device pci 0 on end
-			end
-		end	#PCIE6 WWAN
 		device ref pcie_rp8 on
 			# Enable SD Card PCIE 8 using clk 3
 			register "pch_pcie_rp[PCH_RP(8)]" = "{

src/mainboard/google/brya/variants/brya0/overridetree.cb

@@ -189,7 +189,23 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "reset_off_delay_ms" = "20"
+				# register "reset_delay_ms" = "1000"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp6_rtd3 on
 					probe DB_LTE LTE_PCIE
+				end
+			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
@@ -197,11 +213,11 @@ chip soc/intel/alderlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				register "add_acpi_dma_property" = "true"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 alias rp6_wwan on
+				device generic 0 on
 					probe DB_LTE LTE_PCIE
 				end
 			end
-
+			probe DB_LTE LTE_PCIE
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

src/mainboard/google/brya/variants/brya4es/overridetree.cb

@@ -188,7 +188,23 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "reset_off_delay_ms" = "20"
+				# register "reset_delay_ms" = "1000"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp6_rtd3 on
 					probe DB_LTE LTE_PCIE
+				end
+			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
@@ -196,10 +212,11 @@ chip soc/intel/alderlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				register "add_acpi_dma_property" = "true"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 alias rp6_wwan on
+				device generic 0 on
 					probe DB_LTE LTE_PCIE
 				end
 			end
+			probe DB_LTE LTE_PCIE
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

src/mainboard/google/brya/variants/redrix/overridetree.cb

@@ -174,7 +174,23 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "reset_off_delay_ms" = "20"
+				# register "reset_delay_ms" = "1000"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp6_rtd3 on
 					probe DB_LTE LTE_PCIE
+				end
+			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
@@ -182,10 +198,11 @@ chip soc/intel/alderlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				register "add_acpi_dma_property" = "true"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 alias rp6_wwan on
+				device generic 0 on
 					probe DB_LTE LTE_PCIE
 				end
 			end
+			probe DB_LTE LTE_PCIE
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer

src/mainboard/google/brya/variants/redrix4es/overridetree.cb

@@ -160,7 +160,23 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp6 on
+			# Enable WWAN PCIE 6 using clk 5
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 5,
+				.clk_req = 5,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+				register "reset_off_delay_ms" = "20"
+				# register "reset_delay_ms" = "1000"
+				register "srcclk_pin" = "5"
+				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
+				register "skip_on_off_support" = "true"
+				device generic 0 alias rp6_rtd3 on
 					probe DB_LTE LTE_PCIE
+				end
+			end
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
@@ -168,10 +184,11 @@ chip soc/intel/alderlake
 				register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
 				register "add_acpi_dma_property" = "true"
 				use rp6_rtd3 as rtd3dev
-				device generic 0 alias rp6_wwan on
+				device generic 0 on
 					probe DB_LTE LTE_PCIE
 				end
 			end
+			probe DB_LTE LTE_PCIE
 		end
 		device ref tcss_dma0 on
 			chip drivers/intel/usb4/retimer