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nb/intel/x4x: Add a convenient macro to loop over bytelanes

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During raminit a lot of procedures need to be done for each bytelane.

Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
2017-11-05 05:56:34 +01:00
committed by Patrick Georgi
parent 1994e448be
commit 276049f9ee
4 changed files with 70 additions and 68 deletions
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6
src/northbridge/intel/x4x/rcven.c
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@@ -313,7 +313,7 @@ void rcven(struct sysinfo *s)
* unitialised.
*/
u32 addr = 0;
struct rec_timing timing[8];
struct rec_timing timing[TOTAL_BYTELANES];
u8 mincoarse;
MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc;
@@ -329,7 +329,7 @@ void rcven(struct sysinfo *s)
addr = test_address(channel, rank);
break;
}
for (lane = 0; lane < 8; lane++) {
FOR_EACH_BYTELANE(lane) {
printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n",
channel, lane, addr);
timing[lane].coarse = (s->selected_timings.CAS + 1);
@@ -365,7 +365,7 @@ void rcven(struct sysinfo *s)
s->rcven_t[channel].min_common_coarse = mincoarse;
printk(BIOS_DEBUG, "Receive enable, final timings:\n");
/* Normalise coarse */
for (lane = 0; lane < 8; lane++) {
FOR_EACH_BYTELANE(lane) {
if (timing[lane].coarse == 0)
reg8 = 0;
else