src/cpu: Improve code formatting

Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16391
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Antonello Dettori <dev@dettori.io>

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -200,7 +200,7 @@ ap_init:
 	post_code(0x27)
 
 	/* Do not disable cache (so BSP can enable it). */
-        movl	%cr0, %eax
+	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -72,7 +72,7 @@ static void configure_c_states(void)
 	msr.lo &= ~(1 << 9); // Issue a  single stop grant cycle upon stpclk
 	msr.lo |= (1 << 3); // Dynamic L2
 
-        /* Number of supported C-States */
+	/* Number of supported C-States */
 	msr.lo &= ~7;
 	msr.lo |= HIGHEST_CLEVEL; // support at most C3