From 27753e2b4f9bb42aa58621edf7c13d375a4c413d Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 4 Jun 2020 08:40:35 -0600 Subject: [PATCH] lemp9: enable s0ix and c6dram --- src/mainboard/system76/lemp9/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 201ed3f9bc..dc72b32164 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -13,8 +13,8 @@ chip soc/intel/cannonlake register "SendVrMbxCmd" = "2" # ACPI (soc/intel/cannonlake/acpi.c) - # Disable s0ix - register "s0ix_enable" = "0" + # Enable s0ix + register "s0ix_enable" = "1" # PM Timer Enabled register "PmTimerDisabled" = "0" @@ -37,7 +37,7 @@ chip soc/intel/cannonlake # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) # Serial I/O @@ -184,9 +184,9 @@ chip soc/intel/cannonlake # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - register "deep_sx_config" = "DSX_EN_WAKE_PIN" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" # PM Util (soc/intel/cannonlake/pmutil.c) # GPE configuration